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ORCIDPasquale Corsonello
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- affiliation: University of Calabria, Cosenza, Italy
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2020 – today
- 2024
[j65]Fanny Spagnolo, Pasquale Corsonello, Fabio Frustaci, Stefania Perri:
Efficient implementation of signed multipliers on FPGAs. Comput. Electr. Eng. 116: 109217 (2024)- [j64]Cosimo Ieracitano
, Nadia Mammone, Fanny Spagnolo, Fabio Frustaci, Stefania Perri, Pasquale Corsonello, Francesco Carlo Morabito:
An explainable embedded neural system for on-board ship detection from optical satellite imagery. Eng. Appl. Artif. Intell. 133: 108517 (2024) - [j63]Fanny Spagnolo, Pasquale Corsonello, Fabio Frustaci, Stefania Perri:
Approximate bilateral filters for real-time and low-energy imaging applications on FPGAs. J. Supercomput. 80(11): 15894-15916 (2024) - [j62]Fanny Spagnolo, Stefania Perri, Massimo Vatalaro, Fabio Frustaci, Felice Crupi, Pasquale Corsonello:
Exploring the Usage of Fast Carry Chains to Implement Multistage Ring Oscillators on FPGAs: Design and Characterization. IEEE Trans. Very Large Scale Integr. Syst. 32(8): 1472-1484 (2024) - [c52]Fanny Spagnolo, Pasquale Corsonello, Fabio Frustaci, Stefania Perri:
KIT: Kernel Isotropic Transformation of Bilateral Filters for Image Denoising on FPGA. FPL 2024: 19-23 - 2023
- [j61]Fanny Spagnolo, Pasquale Corsonello, Fabio Frustaci, Stefania Perri:
Design of Approximate Bilateral Filters for Image Denoising on FPGAs. IEEE Access 11: 1990-2000 (2023) - [j60]Stefania Perri, Fanny Spagnolo, Fabio Frustaci, Pasquale Corsonello:
Design of Leading Zero Counters on FPGAs. IEEE Embed. Syst. Lett. 15(3): 149-152 (2023) - [j59]Fabio Frustaci, Fanny Spagnolo, Stefania Perri, Pasquale Corsonello:
A High-Speed FPGA-Based True Random Number Generator Using Metastability With Clock Managers. IEEE Trans. Circuits Syst. II Express Briefs 70(2): 756-760 (2023) - [c51]Bharat Lal, Miguel Heredia Conde, Pasquale Corsonello, Raffaele Gravina:
Secure and Energy-Efficient ECG Signal Monitoring in the IoT Healthcare using Compressive Sensing. DASC/PiCom/CBDCom/CyberSciTech 2023: 333-339 - [c50]Bharat Lal, Qimeng Li, Pasquale Corsonello, Raffaele Gravina:
Abnormal ECG Detection in Wearable Devices Using Compressed Learning. ICNSC 2023: 1-6 - 2022
- [j58]Fanny Spagnolo, Stefania Perri, Pasquale Corsonello:
Approximate Down-Sampling Strategy for Power-Constrained Intelligent Systems. IEEE Access 10: 7073-7081 (2022) - [j57]Fabio Frustaci, Fanny Spagnolo, Stefania Perri, Giuseppe Cocorullo, Pasquale Corsonello:
Robust and High-Performance Machine Vision System for Automatic Quality Inspection in Assembly Processes. Sensors 22(8): 2839 (2022) - [j56]Fanny Spagnolo, Stefania Perri, Pasquale Corsonello:
Aggressive Approximation of the SoftMax Function for Power-Efficient Hardware Implementations. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 1652-1656 (2022) - [j55]Stefania Perri, Fanny Spagnolo, Fabio Frustaci, Pasquale Corsonello:
Multibit Full Comparator Logic in Quantum-Dot Cellular Automata. IEEE Trans. Circuits Syst. II Express Briefs 69(11): 4508-4512 (2022) - [c49]Fanny Spagnolo, Salim Ullah, Pasquale Corsonello, Akash Kumar:
ERMES: Efficient Racetrack Memory Emulation System based on FPGA. FPL 2022: 342-349 - [c48]Mario Andrea Sangiovanni, Fanny Spagnolo, Pasquale Corsonello:
Hardware-Oriented Multi-Exposure Fusion Approach for Real-Time Video Processing on FPGA. PRIME 2022: 129-132 - [c47]Andrea Migali, Fanny Spagnolo, Pasquale Corsonello:
Heterogeneous FPGA-based System for Real-Time Drowsiness Detection. PRIME 2022: 169-172 - 2021
- [j54]Stefania Perri, Fanny Spagnolo, Fabio Frustaci, Pasquale Corsonello:
Accuracy Improved Low-Energy Multi-Bit Approximate Adders in QCA. IEEE Trans. Circuits Syst. II Express Briefs 68(11): 3456-3460 (2021) - 2020
- [j53]Stefania Perri, Fanny Spagnolo, Fabio Frustaci, Pasquale Corsonello:
Parallel architecture of power-of-two multipliers for FPGAs. IET Circuits Devices Syst. 14(3): 381-389 (2020) - [j52]Fanny Spagnolo, Stefania Perri, Pasquale Corsonello:
Design of a real-time face detection architecture for heterogeneous systems-on-chips. Integr. 74: 1-10 (2020) - [j51]Stefania Perri, Cristian Sestito, Fanny Spagnolo, Pasquale Corsonello:
Efficient Deconvolution Architecture for Heterogeneous Systems-on-Chip. J. Imaging 6(9): 85 (2020) - [j50]Stefania Perri, Fabio Frustaci, Fanny Spagnolo, Pasquale Corsonello:
Stereo vision architecture for heterogeneous systems-on-chip. J. Real Time Image Process. 17(2): 393-415 (2020) - [j49]Fabio Frustaci, Stefania Perri, Pasquale Corsonello, Massimo Alioto:
Approximate Multipliers With Dynamic Truncation for Energy Reduction via Graceful Quality Degradation. IEEE Trans. Circuits Syst. 67-II(12): 3427-3431 (2020) - [c46]Cristian Sestito, Fanny Spagnolo, Pasquale Corsonello, Stefania Perri:
An Efficient Convolution Engine based on the À-trous Spatial Pyramid Pooling. ASAP 2020: 77-80 - [c45]Fanny Spagnolo, Fabio Frustaci, Stefania Perri, Pasquale Corsonello:
A High-Performance and Power-Efficient SIMD Convolution Engine for FPGAs. ICECS 2020: 1-4 - [c44]Fanny Spagnolo, Stefania Perri, Fabio Frustaci, Pasquale Corsonello:
Reconfigurable Convolution Architecture for Heterogeneous Systems-on-Chip. MECO 2020: 1-5
2010 – 2019
- 2019
- [j48]Giuseppe Cocorullo, Pasquale Corsonello, Fabio Frustaci, Lorena-de-los-Angeles Guachi-Guachi, Stefania Perri:
Multimodal background subtraction for high-performance embedded systems. J. Real Time Image Process. 16(5): 1407-1423 (2019) - [j47]Fanny Spagnolo, Stefania Perri, Pasquale Corsonello:
An Efficient Hardware-Oriented Single-Pass Approach for Connected Component Analysis. Sensors 19(14): 3055 (2019) - [j46]Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg, Chip-Hong Chang, Meng-Fan Chang, Yao-Wen Chang, Poki Chen, Pasquale Corsonello, Paolo Crovetti, Shiro Dosho, Rolf Drechsler, Ibrahim Abe M. Elfadel, Ruonan Han, Masanori Hashimoto, Chun-Huat Heng, Deukhyoun Heo, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Ajay Joshi, Rajiv V. Joshi, Tanay Karnik, Chulwoo Kim, Tony Tae-Hyoung Kim, Jaydeep Kulkarni, Volkan Kursun, Yoonmyung Lee, Hai Helen Li, Huawei Li, Prabhat Mishra, Baker Mohammad, Mehran Mozaffari Kermani, Makoto Nagata, Koji Nii, Partha Pratim Pande, Bipul C. Paul, Vasilis F. Pavlidis, José Pineda de Gyvez, Ioannis Savidis, Patrick Schaumont, Fabio Sebastiano, Anirban Sengupta, Mingoo Seok, Mircea R. Stan, Mark M. Tehranipoor, Aida Todri-Sanial, Marian Verhelst, Valerio Vignoli, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Jun Zhou, Mark Zwolinski, Stacey Weber:
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. IEEE Trans. Very Large Scale Integr. Syst. 27(2): 253-280 (2019) - [j45]Fabio Frustaci, Stefania Perri, Pasquale Corsonello, Massimo Alioto:
Energy-Quality Scalable Adders Based on Nonzeroing Bit Truncation. IEEE Trans. Very Large Scale Integr. Syst. 27(4): 964-968 (2019) - [c43]Fanny Spagnolo, Pasquale Corsonello, Stefania Perri:
Efficient Architecture for Integral Image Computation on Heterogeneous FPGAs. PRIME 2019: 229-232 - 2018
- [c42]Fanny Spagnolo, Stefania Perri, Fabio Frustaci, Pasquale Corsonello:
Connected Component Analysis for Traffic Sign Recognition Embedded Processing Systems. ICECS 2018: 749-752 - [c41]Fanny Spagnolo, Stefania Perri, Fabio Frustaci, Pasquale Corsonello:
Designing Fast Convolutional Engines for Deep Learning Applications. ICECS 2018: 753-756 - [c40]Stefania Perri, Fabio Frustaci, Fanny Spagnolo, Pasquale Corsonello:
Design of Real-Time FPGA-based Embedded System for Stereo Vision. ISCAS 2018: 1-5 - 2017
- [j44]Giuseppe Cocorullo, Pasquale Corsonello, Fabio Frustaci, Stefania Perri:
Design of Efficient BCD Adders in Quantum-Dot Cellular Automata. IEEE Trans. Circuits Syst. II Express Briefs 64-II(5): 575-579 (2017) - [j43]Krishnendu Chakrabarty, Massimo Alioto, Bevan M. Baas, Chirn Chye Boon, Meng-Fan Chang, Naehyuck Chang, Yao-Wen Chang, Chip-Hong Chang, Shih-Chieh Chang, Poki Chen, Masud H. Chowdhury, Pasquale Corsonello, Ibrahim Abe M. Elfadel, Said Hamdioui, Masanori Hashimoto, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Rajiv V. Joshi, Tanay Karnik, Mehran Mozaffari Kermani, Chulwoo Kim, Tae-Hyoung Kim, Jaydeep P. Kulkarni, Eren Kursun, Erik Larsson, Hai (Helen) Li, Huawei Li, Patrick P. Mercier, Prabhat Mishra, Makoto Nagata, Arun S. Natarajan, Koji Nii, Partha Pratim Pande, Ioannis Savidis, Mingoo Seok, Sheldon X.-D. Tan, Mark M. Tehranipoor, Aida Todri-Sanial, Miroslav N. Velev, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Stacey Weber Jackson:
Editorial. IEEE Trans. Very Large Scale Integr. Syst. 25(1): 1-20 (2017) - 2016
- [j42]Giuseppe Cocorullo, Pasquale Corsonello, Fabio Frustaci, Stefania Perri:
Design of efficient QCA multiplexers. Int. J. Circuit Theory Appl. 44(3): 602-615 (2016) - [j41]Giuseppe Cocorullo, Pasquale Corsonello, Fabio Frustaci, Stefania Perri:
An efficient hardware-oriented stereo matching algorithm. Microprocess. Microsystems 46: 21-33 (2016) - 2015
- [j40]Luca Magnelli, Felice Crupi, Pasquale Corsonello, Giuseppe Iannaccone:
A sub-1 V nanopower temperature-compensated sub-threshold CMOS voltage reference with 0.065%/V line sensitivity. Int. J. Circuit Theory Appl. 43(4): 421-426 (2015) - [j39]Pasquale Corsonello, Fabio Frustaci, Stefania Perri:
Power supply noise in accurate delay model for the sub-threshold domain. Integr. 50: 127-136 (2015) - [j38]Marco Lanuzza, Pasquale Corsonello, Stefania Perri:
Fast and Wide Range Voltage Conversion in Multisupply Voltage Designs. IEEE Trans. Very Large Scale Integr. Syst. 23(2): 388-391 (2015) - [j37]Pasquale Corsonello, Fabio Frustaci, Stefania Perri:
Low-Leakage SRAM Wordline Drivers for the 28-nm UTBB FDSOI Technology. IEEE Trans. Very Large Scale Integr. Syst. 23(12): 3133-3137 (2015) - [c39]Pasquale Corsonello, Stefania Perri, Fabio Frustaci:
Exploring well configurations for voltage level converter design in 28 nm UTBB FDSOI technology. ICCD 2015: 499-504 - [c38]Sandra Costanzo, Francesca Venneri, Antonio Raffo, Giuseppe Di Massa, Pasquale Corsonello:
Novel Varactor-Loaded Phasing Line for Reflectarray Unit Cell with Large Reconfigurability Frequency Range. WorldCIST (2) 2015: 3-9 - 2014
- [j36]Pasquale Corsonello, Marco Lanuzza, Stefania Perri:
Gate-level body biasing technique for high-speed sub-threshold CMOS logic gates. Int. J. Circuit Theory Appl. 42(1): 65-70 (2014) - [j35]Fabio Frustaci, Marco Lanuzza, Stefania Perri, Pasquale Corsonello:
Analyzing noise robustness of wide fan-in dynamic logic gates under process variations. Int. J. Circuit Theory Appl. 42(5): 452-467 (2014) - [j34]Stefania Perri, Marco Lanuzza, Pasquale Corsonello:
Design of high-speed low-power parallel-prefix adder trees in nanometer technologies. Int. J. Circuit Theory Appl. 42(7): 731-743 (2014) - [j33]Pasquale Corsonello, Fabio Frustaci, Marco Lanuzza, Stefania Perri:
Over/Undershooting Effects in Accurate Buffer Delay Model for Sub-Threshold Domain. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(5): 1456-1464 (2014) - [j32]Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo:
Area-Delay Efficient Binary Adders in QCA. IEEE Trans. Very Large Scale Integr. Syst. 22(5): 1174-1179 (2014) - [c37]Lorena Guachi, Giuseppe Cocorullo, Pasquale Corsonello, Fabio Frustaci, Stefania Perri:
A novel background subtraction method based on color invariants and grayscale levels. ICCST 2014: 1-5 - 2013
- [j31]Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo:
Adaptive Census Transform: A novel hardware-oriented stereovision algorithm. Comput. Vis. Image Underst. 117(1): 29-41 (2013) - 2012
- [j30]Fabio Frustaci, Stefania Perri, Marco Lanuzza, Pasquale Corsonello:
Energy-efficient single-clock-cycle binary comparator. Int. J. Circuit Theory Appl. 40(3): 237-246 (2012) - [j29]Paolo Zicari, Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo:
Low-cost FPGA stereo vision system for real time disparity maps calculation. Microprocess. Microsystems 36(4): 281-288 (2012) - [j28]Marco Lanuzza, Raffaele De Rose, Fabio Frustaci, Stefania Perri, Pasquale Corsonello:
Comparative analysis of yield optimized pulsed flip-flops. Microelectron. Reliab. 52(8): 1679-1689 (2012) - [j27]Fabio Frustaci, Pasquale Corsonello, Stefania Perri:
Analytical Delay Model Considering Variability Effects in Subthreshold Domain. IEEE Trans. Circuits Syst. II Express Briefs 59-II(3): 168-172 (2012) - [j26]Marco Lanuzza, Pasquale Corsonello, Stefania Perri:
Low-Power Level Shifter for Multi-Supply Voltage Designs. IEEE Trans. Circuits Syst. II Express Briefs 59-II(12): 922-926 (2012) - 2011
- [j25]Stefania Perri, Pasquale Corsonello:
Efficient memory architecture for image processing. Int. J. Circuit Theory Appl. 39(3): 351-356 (2011) - [j24]Stefania Perri, Pasquale Corsonello:
Fast-squarer circuits using 3-bit-scan without overlapping bits. Int. J. Circuit Theory Appl. 39(10): 1037-1047 (2011) - [j23]Luca Magnelli, Felice Crupi, Pasquale Corsonello, Calogero Pace, Giuseppe Iannaccone:
A 2.6 nW, 0.45 V Temperature-Compensated Subthreshold CMOS Voltage Reference. IEEE J. Solid State Circuits 46(2): 465-474 (2011) - [j22]Fabio Frustaci, Massimo Alioto, Pasquale Corsonello:
Tapered-Vth Approach for Energy-Efficient CMOS Buffers. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(11): 2698-2707 (2011) - [c36]Fabio Frustaci, Pasquale Corsonello, Massimo Alioto:
Optimization and evaluation of tapered-VTH approach for energy-efficient CMOS buffers. ECCTD 2011: 592-595 - [c35]Fabio Frustaci, Pasquale Corsonello, Massimo Alioto:
Tapered-VTH CMOS buffer design for improved energy efficiency in deep nanometer technology. ISCAS 2011: 2075-2078 - 2010
- [j21]Marco Lanuzza, Paolo Zicari, Fabio Frustaci, Stefania Perri, Pasquale Corsonello:
Exploiting Self-Reconfiguration Capability to Improve SRAM-based FPGA Robustness in Space and Avionics Applications. ACM Trans. Reconfigurable Technol. Syst. 4(1): 8:1-8:22 (2010) - [c34]Sohit Solanki, Fabio Frustaci, Pasquale Corsonello:
A Low-Leakage Single-Ended 6T SRAM Cell. ICETET 2010: 698-702 - [c33]Sumit Kansal, Marco Lanuzza, Pasquale Corsonello:
Impact of Random Process Variations on Different 65nm SRAM Cell Topologies. ICETET 2010: 703-706 - [c32]Fabio Frustaci, Stefania Perri, Marco Lanuzza, Pasquale Corsonello:
A new low-power high-speed single-clock-cycle binary comparator. ISCAS 2010: 317-320 - [c31]Marco Lanuzza, Raffaele De Rose, Fabio Frustaci, Stefania Perri, Pasquale Corsonello:
Impact of Process Variations on Flip-Flops Energy and Timing Characteristics. ISVLSI 2010: 458-459 - [c30]Marco Lanuzza, Raffaele De Rose, Fabio Frustaci, Stefania Perri, Pasquale Corsonello:
Impact of Process Variations on Pulsed Flip-Flops: Yield Improving Circuit-Level Techniques and Comparative Analysis. PATMOS 2010: 180-189
2000 – 2009
- 2009
- [j20]Fabio Frustaci, Marco Lanuzza, Paolo Zicari, Stefania Perri, Pasquale Corsonello:
Low-power split-path data-driven dynamic logic. IET Circuits Devices Syst. 3(6): 303-312 (2009) - [j19]Sohan Purohit, Marco Lanuzza, Stefania Perri, Pasquale Corsonello, Martin Margala:
Design and Evaluation of an Energy-Delay-Area Efficient Datapath for Coarse-Grain Reconfigurable Computing Systems. J. Low Power Electron. 5(3): 326-338 (2009) - [j18]Fabio Frustaci, Marco Lanuzza, Paolo Zicari, Stefania Perri, Pasquale Corsonello:
Designing High-Speed Adders in Power-Constrained Environments. IEEE Trans. Circuits Syst. II Express Briefs 56-II(2): 172-176 (2009) - [c29]Marco Lanuzza, Paolo Zicari, Fabio Frustaci, Stefania Perri, Pasquale Corsonello:
An Efficient and Low-Cost Design Methodology to Improve SRAM-Based FPGA Robustness in Space and Avionics Applications. ARC 2009: 74-84 - [c28]Sohan Purohit, Martin Margala, Marco Lanuzza, Pasquale Corsonello:
New performance/power/area efficient, reliable full adder design. ACM Great Lakes Symposium on VLSI 2009: 493-498 - [c27]Aakash Jain, Giovanni Staino, Pasquale Corsonello:
Quad-Port Memory Blocks in Radiation-Tolerant FPGAs: An Application for Image Processing Systems. ICETET 2009: 368-371 - [c26]Sohan Purohit, Marco Lanuzza, Stefania Perri, Pasquale Corsonello, Martin Margala:
Design-Space Exploration of Energy-Delay-Area Efficient Coarse-Grain Reconfigurable Datapath. VLSI Design 2009: 45-50 - 2008
- [j17]Fabio Frustaci, Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo:
High-performance noise-tolerant circuit techniques for CMOS dynamic logic. IET Circuits Devices Syst. 2(6): 537-548 (2008) - [j16]Paolo Zicari, Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo:
A matrix product accelerator for field programmable systems on chip. Microprocess. Microsystems 32(2): 53-67 (2008) - [j15]Paolo Zicari, Emanuele Sciagura, Stefania Perri, Pasquale Corsonello:
A programmable carrier phase independent symbol timing recovery circuit for QPSK/OQPSK signals. Microprocess. Microsystems 32(8): 437-446 (2008) - [j14]Stefania Perri, Pasquale Corsonello:
Fast Low-Cost Implementation of Single-Clock-Cycle Binary Comparator. IEEE Trans. Circuits Syst. II Express Briefs 55-II(12): 1239-1243 (2008) - [c25]Fabio Frustaci, Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo:
A New Dynamic Logic Circuit Design for an Effective Trade-Off between Noise-Immunity, Performance and Energy Dissipation. PATMOS 2008: 277-286 - [c24]Marco Lanuzza, Stefania Perri, Pasquale Corsonello, Martin Margala:
Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing. PATMOS 2008: 297-306 - [c23]Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala, Pasquale Corsonello:
Power-Efficient High Throughput Reconfigurable Datapath Design for Portable Multimedia Devices. ReConFig 2008: 217-222 - [c22]Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala, Pasquale Corsonello:
Power/throughput/area efficient PIM-based reconfigurable array for parallel processing. SoCC 2008: 375-378 - 2007
- [j13]Stefania Perri, Pasquale Corsonello:
VLSI implementations of efficient isotropic flexible 2D convolvers. IET Circuits Devices Syst. 1(4): 263-269 (2007) - [c21]Marco Lanuzza, Stefania Perri, Pasquale Corsonello, Martin Margala:
A New Reconfigurable Coarse-Grain Architecture for Multimedia Applications. AHS 2007: 119-126 - [c20]Emanuele Sciagura, Paolo Zicari, Stefania Perri, Pasquale Corsonello:
An efficient and optimized FPGA Feedback M-PSK Symbol Timing Recovery Architecture based on the Gardner Timing Error Detector. DSD 2007: 102-108 - [c19]Pasquale Corsonello, Stefania Perri, Giovanni Staino, Marco Lanuzza, Giuseppe Cocorullo:
Design and Implementation of a 90nm Low bit-rate Image Compression Core. DSD 2007: 383-389 - [c18]Marco Lanuzza, Stefania Perri, Pasquale Corsonello:
MORA: A New Coarse-Grain Reconfigurable Array for High Throughput Multimedia Processing. SAMOS 2007: 159-168 - 2006
- [j12]Stefania Perri, Maria Antonia Iachino, Pasquale Corsonello:
Simd Multipliers for Accelerating Embedded Processors in FPGAS. J. Circuits Syst. Comput. 15(4): 537-550 (2006) - [j11]Pasquale Corsonello, Stefania Perri, Giovanni Staino, Marco Lanuzza, Giuseppe Cocorullo:
Low bit rate image compression core for onboard space applications. IEEE Trans. Circuits Syst. Video Technol. 16(1): 114-128 (2006) - [j10]Fabio Frustaci, Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo:
Techniques for Leakage Energy Reduction in Deep Submicrometer Cache Memories. IEEE Trans. Very Large Scale Integr. Syst. 14(11): 1238-1249 (2006) - [c17]Paolo Zicari, Pasquale Corsonello, Stefania Perri:
An Efficient Bit-Detection and Timing Recovery Circuit for FPGAs. ICECS 2006: 168-171 - [c16]Stefania Perri, Daniela Colonna, Paolo Zicari, Pasquale Corsonello:
SAD-Based Stereo Matching Circuit for FPGAs. ICECS 2006: 846-849 - [c15]Pasquale Corsonello, Stefania Perri, Martin Margala:
An integrated countermeasure against differential power analysis for secure smart-cards. ISCAS 2006 - [c14]Fabio Frustaci, Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo:
Leakage energy reduction techniques in deep submicron cache memories: a comparative study. ISCAS 2006 - 2005
- [j9]Pasquale Corsonello, Stefania Perri:
Efficient Reconfigurable Manchester Adders for Low-power Media Processing. J. Circuits Syst. Comput. 14(1): 57-64 (2005) - [j8]Pasquale Corsonello, Stefania Perri, Paolo Zicari, Giuseppe Cocorullo:
Microprocessor-based FPGA implementation of SPIHT image compression subsystems. Microprocess. Microsystems 29(6): 299-305 (2005) - [j7]Stefania Perri, Marco Lanuzza, Pasquale Corsonello, Giuseppe Cocorullo:
A high-performance fully reconfigurable FPGA-based 2D convolution processor. Microprocess. Microsystems 29(8-9): 381-391 (2005) - [j6]Pasquale Corsonello, Stefania Perri, Martin Margala:
Efficient Addition Circuits for Modular Design of Processors-in-Memory. IEEE Trans. Circuits Syst. I Regul. Pap. 52-I(8): 1557-1567 (2005) - [c13]Marco Lanuzza, Stefania Perri, Martin Margala, Pasquale Corsonello:
Low-Cost Fully Reconfigurable Data-Path for FPGA-Based Multimedia Processor. FPL 2005: 13-18 - [c12]Marco Lanuzza, Martin Margala, Pasquale Corsonello:
Cost-effective low-power processor-in-memory-based reconfigurable datapath for multimedia applications. ISLPED 2005: 161-166 - [c11]Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo:
Fast Low-Power 64-Bit Modular Hybrid Adder. PATMOS 2005: 609-617 - 2004
- [j5]Stefania Perri, Pasquale Corsonello, Maria Antonia Iachino, Marco Lanuzza, Giuseppe Cocorullo:
Variable precision arithmetic circuits for FPGA-based multimedia processors. IEEE Trans. Very Large Scale Integr. Syst. 12(9): 995-999 (2004) - [c10]Pasquale Corsonello, Stefania Perri, Vitit Kantabutra:
Area- and Power-Reduced Standard-Cell Spanning Tree Adders. ESA/VLSI 2004: 343-352 - 2003
- [j4]Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo:
A high-speed energy-efficient 64-bit reconfigurable binary adder. IEEE Trans. Very Large Scale Integr. Syst. 11(5): 939-943 (2003) - [c9]Pasquale Corsonello, Stefania Perri, Maria Antonia Iachino, Giuseppe Cocorullo:
Variable Precision Multipliers for FPGA-Based Reconfigurable Computing Systems. FPL 2003: 661-669 - [c8]Stefania Perri, Pasquale Corsonello, Giovanni Staino:
A low-power sub-nanosecond standard-cells based adder. ICECS 2003: 296-299 - 2002
- [j3]Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo:
VLSI circuits for low-power high-speed asynchronous addition. IEEE Trans. Very Large Scale Integr. Syst. 10(5): 608-613 (2002) - [c7]Stefania Perri, Maria Antonia Iachino, Pasquale Corsonello:
Speed-efficient wide adders for VIRTEX FPGAs. ICECS 2002: 599-602 - [c6]Pasquale Corsonello, Giandomenico Spezzano, Giovanni Staino, Domenico Talia:
Efficient Implementation of Cellular Algorithms on Reconfigurable Hardware. PDP 2002: 211-218 - 2001
- [c5]Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo, Gregorio Cappuccino, Giovanni Staino:
VLSI implementation of a fully static CMOS 56-bit self-timed adder using overlapped execution circuits. ICECS 2001: 723-727 - [c4]Gregorio Cappuccino, Pasquale Corsonello, Giuseppe Cocorullo, Stefania Perri, Giovanni Staino:
Dynamic power of CMOS gates driving lossy transmission lines. ICECS 2001: 1579-1582 - 2000
- [j2]Pasquale Corsonello, Stefania Perri, G. Cororullo:
Area-time-power tradeoff in cellular arrays VLSI implementations. IEEE Trans. Very Large Scale Integr. Syst. 8(5): 614-624 (2000) - [c3]Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo:
Designing High-Speed Asynchronous Pipelines. EUROMICRO 2000: 1394-1399 - [c2]Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo:
VLSI Implementation of a Low-Power High-Speed Self-Timed Adder. PATMOS 2000: 195-204
1990 – 1999
- 1999
- [c1]Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo:
A 56-bit self-timed adder for high speed asynchronous datapath. ICECS 1999: 37-41 - 1998
- [j1]Gregorio Cappuccino, Pasquale Corsonello, Giuseppe Cocorullo:
High performance VLSI modules for division and square root. Microprocess. Microsystems 22(5): 239-246 (1998)
Coauthor Index
[j65] [j64] [j63] [j62] [c52] [j61] [j60] [j59] [j58] [j57] [j56] [j55] [j54] [j53] [j52] [j51] [j50] [j49] [c46] [c45] [c44] [j48] [j47] [j45] [c43] [c42] [c41] [c40] [j44] [j42] [j41] [j39] [j38] [j37] [c39] [j36] [j35] [j34] [j33] [j32] [c37] [j31] [j30] [j29] [j28] [j27] [j26] [j25] [j24] [j21] [c32] [c31] [c30] [j20] [j19] [j18] [c29] [c26] [j17] [j16] [j15] [j14] [c25] [c24] [j13] [c21] [c20] [c19] [c18] [j12] [j11] [j10] [c17] [c16] [c15] [c14] [j9] [j8] [j7] [j6] [c13] [c11] [j5] [c10] [j4] [c9] [c8] [j3] [c7] [c5] [c4] [j2] [c3] [c2] [c1]
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