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ORCIDAnirban Sengupta
This is just a disambiguation page, and is not intended to be the bibliography of an actual person. Any publication listed on this page has not been assigned to an actual author yet. If you know the true author of one of the publications listed below, you are welcome to contact us.
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2020 – today
- 2024
[j90]Anirban Sengupta
, Aditya Anshul:
Watermarking Hardware IPs Using Design Parameter Driven Encrypted Dispersion Matrix With Eigen Decomposition Based Security Framework. IEEE Access 12: 47494-47507 (2024)- [j89]Anirban Sengupta, Rahul Chaurasia:
Secure FFT IP Using C-Way Partitioning-Based Obfuscation and Fingerprint. IEEE Des. Test 41(5): 55-64 (2024) - [j88]Anirban Sengupta, Aditya Anshul:
A Survey of High-Level Synthesis-Based Hardware (IP) Watermarking Approaches. IEEE Des. Test 41(6): 70-83 (2024) - [j87]Mahendra Rathor, Anirban Sengupta:
Revisiting Black-Hat HLS: A Lightweight Countermeasure to HLS-Aided Trojan Attack. IEEE Embed. Syst. Lett. 16(2): 170-173 (2024) - [j86]Rahul Chaurasia, Anirban Sengupta:
Multi-cut based architectural obfuscation and handprint biometric signature for securing transient fault detectable IP cores during HLS. Integr. 95: 102114 (2024) - [j85]Anirban Sengupta, Aditya Anshul:
Hardware Security of Image Processing Cores Against IP Piracy Using PSO-Based HLS-Driven Multi-Stage Encryption Fused with Fingerprint Signature. SN Comput. Sci. 5(7): 941 (2024) - [j84]Anirban Sengupta, Dushmanta Kumar Das:
Delay-Dependent Wide-Area Damping Controller Considering Actuator Saturation and Communication Failure. IEEE Trans. Control. Netw. Syst. 11(2): 977-988 (2024) - [j83]Mahendra Rathor, Aditya Anshul, Anirban Sengupta:
Securing Reusable IP Cores Using Voice Biometric Based Watermark. IEEE Trans. Dependable Secur. Comput. 21(4): 2735-2749 (2024) - [c75]Anirban Sengupta, Vishal Chourasia, Aditya Anshul:
HLS Scheduling Driven Encoded Watermarking for Secure Convolutional Layer IP Design in CNN. ICCE-Taiwan 2024: 587-588 - [c74]Anirban Sengupta, Vishal Chourasia, Aditya Anshul, Nitish Kumar:
Robust Watermarking of Loop Unrolled Convolution Layer IP Design for CNN using 4-variable Encoded Register Allocation. ICCE-Taiwan 2024: 589-590 - [c73]Vishal Chourasia, Anirban Sengupta, Rahul Chaurasia:
HLS based Hardware Watermarking of Blur, Embossment and Sharpening Filters Using Fused Ocular Biometrics and Digital Signature. SOCC 2024: 143-148 - 2023
- [j82]Mahendra Rathor, Aditya Anshul, K. Bharath, Rahul Chaurasia, Anirban Sengupta:
Quadruple phase watermarking during high level synthesis for securing reusable hardware intellectual property cores. Comput. Electr. Eng. 105: 108476 (2023) - [j81]Anirban Sengupta, Rahul Chaurasia, K. Bharath:
Exploring unified biometrics with encoded dictionary for hardware security of fault secured IP core designs. Comput. Electr. Eng. 111(Part A): 108928 (2023) - [j80]Aditya Anshul, Anirban Sengupta:
PSO based exploration of multi-phase encryption based secured image processing filter hardware IP core datapath during high level synthesis. Expert Syst. Appl. 223: 119927 (2023) - [j79]Anirban Sengupta, Mahendra Rathor, Rahul Chaurasia:
Biometrics for Hardware Security and Trust: Discussion and Analysis. IT Prof. 25(4): 36-44 (2023) - [j78]Aditya Anshul, Anirban Sengupta:
Exploration of optimal crypto-chain signature embedded secure JPEG-CODEC hardware IP during high level synthesis. Microprocess. Microsystems 102: 104916 (2023) - [j77]Anirban Sengupta, Aditya Anshul, Rahul Chaurasia:
Exploration of optimal functional Trojan-resistant hardware intellectual property (IP) core designs during high level synthesis. Microprocess. Microsystems 103: 104973 (2023) - [j76]Rahul Chaurasia, Anirban Sengupta:
Retinal Biometric for Securing JPEG-Codec Hardware IP Core for CE Systems. IEEE Trans. Consumer Electron. 69(3): 441-457 (2023) - [j75]Mahendra Rathor, Anirban Sengupta, Rahul Chaurasia, Aditya Anshul:
Exploring Handwritten Signature Image Features for Hardware Security. IEEE Trans. Dependable Secur. Comput. 20(5): 3687-3698 (2023) - [j74]Anirban Sengupta, Rahul Chaurasia, Aditya Anshul:
Robust Security of Hardware Accelerators Using Protein Molecular Biometric Signature and Facial Biometric Encryption Key. IEEE Trans. Very Large Scale Integr. Syst. 31(6): 826-839 (2023) - [c72]Anirban Sengupta, Rahul Chaurasia, Aditya Anshul:
Hardware Security of Digital Image Filter IP Cores against Piracy using IP Seller's Fingerprint Encrypted Amino Acid Biometric Sample. AsianHOST 2023: 1-6 - [c71]Rahul Chaurasia, Abhinav Reddy Asireddy, Anirban Sengupta:
Fault Secured JPEG-Codec Hardware Accelerator with Piracy Detective Control using Secure Fingerprint Template. DFT 2023: 1-6 - [c70]Anirban Sengupta, Aditya Anshul, Chirag Kothari, Sumer Thakur:
Secured and Optimized Hardware Accelerators using Key-Controlled Encoded Hash Slices and Firefly Algorithm based Exploration. ICM 2023: 149-152 - [c69]Anirban Sengupta, Aditya Anshul, Sumer Thakur, Chirag Kothari:
Fusing IP vendor Palmprint Biometric with Encoded Hash for Hardware IP Core Protection of Image Processing Filters. ICM 2023: 218-221 - [c68]Aditya Anshul, Anirban Sengupta:
Low-Cost Hardware Security of Laplace Edge Detection and Embossment Filter Using HLS Based Encryption and PSO. iSES 2023: 135-140 - [c67]Anirban Sengupta, Aditya Anshul:
Key-Driven Multi-Layered Structural Obfuscation of IP cores using Reconfigurable Obfuscator based Network Challenge and Switch Control Logic. iSES 2023: 141-146 - [c66]Anirban Sengupta, Rahul Chaurasia:
Securing Fault-Detectable CNN Hardware Accelerator Against False Claim of IP Ownership Using Embedded Fingerprint as Countermeasure. iSES 2023: 147-152 - [c65]Rahul Chaurasia, Anirban Sengupta:
Designing Optimized and Secured Reusable Convolutional Hardware Accelerator Against IP Piracy Using Retina Biometrics. iSES 2023: 153-158 - 2022
- [j73]Anirban Sengupta, Rahul Chaurasia:
Securing IP Cores for DSP Applications Using Structural Obfuscation and Chromosomal DNA Impression. IEEE Access 10: 50903-50913 (2022) - [j72]Rahul Chaurasia, Aditya Anshul, Anirban Sengupta, Shikha Gupta:
Palmprint Biometric Versus Encrypted Hash Based Digital Signature for Securing DSP Cores Used in CE Systems. IEEE Consumer Electron. Mag. 11(5): 73-80 (2022) - [j71]Asmita Manna, Anirban Sengupta, Chandan Mazumdar:
A risk-based methodology for privacy requirements elicitation and control selection. Secur. Priv. 5(1) (2022) - [j70]Preetam Mukherjee, Anirban Sengupta, Chandan Mazumdar:
"Security Gap" as a metric for enterprise business processes. Secur. Priv. 5(6) (2022) - [j69]Anirban Sengupta, Rahul Chaurasia:
Secured Convolutional Layer IP Core in Convolutional Neural Network Using Facial Biometric. IEEE Trans. Consumer Electron. 68(3): 291-306 (2022) - [c64]Aditya Anshul, Anirban Sengupta:
IP Core Protection of Image Processing Filters with Multi-Level Encryption and Covert Steganographic Security Constraints. iSES 2022: 83-88 - [c63]Aditya Anshul, K. Bharath, Anirban Sengupta:
Designing Low Cost Secured DSP Core using Steganography and PSO for CE systems. iSES 2022: 95-100 - [c62]Rahul Chaurasia, Anirban Sengupta:
Symmetrical Protection of Ownership Right's for IP Buyer and IP Vendor using Facial Biometric Pairing. iSES 2022: 272-277 - [c61]Rahul Chaurasia, Anirban Sengupta:
Security Vs Design Cost of Signature Driven Security Methodologies for Reusable Hardware IP Core. iSES 2022: 283-288 - [p2]Anirban Sengupta, Mahendra Rathor:
Hardware (IP) Watermarking During Behavioral Synthesis. Behavioral Synthesis for Hardware Security 2022: 119-145 - 2021
- [j68]Anirban Sengupta, Arabinda Mishra, Feng Wang, Muwei Li, Pai-Feng Yang, Li Min Chen, John C. Gore:
Functional networks in non-human primate spinal cord and the effects of injury. NeuroImage 240: 118391 (2021) - [j67]Wei Hu, Chip-Hong Chang, Anirban Sengupta, Swarup Bhunia, Ryan Kastner, Hai Li:
An Overview of Hardware Security and Trust: Threats, Countermeasures, and Design Tools. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(6): 1010-1038 (2021) - [j66]Anirban Sengupta, Rahul Chaurasia, Tarun Reddy:
Contact-Less Palmprint Biometric for Securing DSP Coprocessors Used in CE Systems. IEEE Trans. Consumer Electron. 67(3): 202-213 (2021) - [j65]Arindam Das, Manoj Kumar Gangwar, Devleena Ghosh, Chittaranjan Mandal, Anirban Sengupta, M. Mubashshir Waris:
Automatic Generation of Route Control Chart From Validated Signal Interlocking Plan. IEEE Trans. Intell. Transp. Syst. 22(10): 6516-6525 (2021) - [j64]Anirban Sengupta, Mahendra Rathor:
Facial Biometric for Securing Hardware Accelerators. IEEE Trans. Very Large Scale Integr. Syst. 29(1): 112-123 (2021) - [c60]Anirban Sengupta:
A Stakeholder-Centric Approach for Defining Metrics for Information Security Management Systems. CRiSIS 2021: 57-73 - [c59]Mahendra Rathor, Anirban Sengupta:
Signature Biometric based Authentication of IP Cores for Secure Electronic Systems. iSES 2021: 384-388 - [c58]Rahul Chaurasia, Anirban Sengupta:
Securing Reusable Hardware IP cores using Palmprint Biometric. iSES 2021: 410-413 - 2020
- [j63]Anirban Sengupta, Mahendra Rathor:
Structural Obfuscation and Crypto-Steganography-Based Secured JPEG Compression Hardware for Medical Imaging Systems. IEEE Access 8: 6543-6565 (2020) - [j62]Anirban Sengupta, Mahendra Rathor:
Enhanced Security of DSP Circuits Using Multi-Key Based Structural Obfuscation and Physical-Level Watermarking for Consumer Electronics Systems. IEEE Trans. Consumer Electron. 66(2): 163-172 (2020) - [j61]Mahendra Rathor, Anirban Sengupta:
IP Core Steganography Using Switch Based Key-Driven Hash-Chaining and Encoding for Securing DSP Kernels Used in CE Systems. IEEE Trans. Consumer Electron. 66(3): 251-260 (2020) - [j60]Anirban Sengupta, Mahendra Rathor:
Obfuscated Hardware Accelerators for Image Processing Filters - Application Specific and Functionally Reconfigurable Processors. IEEE Trans. Consumer Electron. 66(4): 386-395 (2020) - [j59]Anirban Sengupta, Mahendra Rathor:
Securing Hardware Accelerators for CE Systems Using Biometric Fingerprinting. IEEE Trans. Very Large Scale Integr. Syst. 28(9): 1979-1992 (2020) - [c57]Puloma Roy, Anirban Sengupta, Chandan Mazumdar:
A Structured Control Selection Methodology for Insider Threat Mitigation. CENTERIS/ProjMAN/HCist 2020: 1187-1195 - [c56]Mahendra Rathor, Pallabi Sarkar, Vipul Kumar Mishra, Anirban Sengupta:
Securing IP Cores in CE Systems using Key-driven Hash-chaining based Steganography. ICCE-Berlin 2020: 1-4
2010 – 2019
- 2019
- [j58]Anirban Sengupta, Mahendra Rathor:
Security of Functionally Obfuscated DSP Core Against Removal Attack Using SHA-512 Based Key Encryption Hardware. IEEE Access 7: 4598-4610 (2019) - [j57]Mahendra Rathor, Anirban Sengupta:
Robust Logic locking for Securing Reusable DSP Cores. IEEE Access 7: 120052-120064 (2019) - [j56]Pallabi Sarkar, Dipanjan Roy, Anirban Sengupta, Mrinal Kanti Naskar:
Signature-Free Watermark for Protecting Digital Signal Processing Cores Used in CE Devices [Hardware Matters]. IEEE Consumer Electron. Mag. 8(1): 92-94 (2019) - [j55]Dipanjan Roy, Anirban Sengupta:
Multilevel Watermark for Protecting DSP Kernel in CE Systems [Hardware Matters]. IEEE Consumer Electron. Mag. 8(2): 100-102 (2019) - [j54]Anirban Sengupta, Deepak Kachave, Dipanjan Roy:
Low Cost Functional Obfuscation of Reusable IP Ores Used in CE Hardware Through Robust Locking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(4): 604-616 (2019) - [j53]Anirban Sengupta, Mahendra Rathor:
Protecting DSP Kernels Using Robust Hologram-Based Obfuscation. IEEE Trans. Consumer Electron. 65(1): 99-108 (2019) - [j52]Anirban Sengupta, E. Ranjith Kumar, N. Prajwal Chandra:
Embedding Digital Signature Using Encrypted-Hashing for Protection of DSP Cores in CE. IEEE Trans. Consumer Electron. 65(3): 398-407 (2019) - [j51]Anirban Sengupta, Mahendra Rathor:
IP Core Steganography for Protecting DSP Kernels Used in CE Systems. IEEE Trans. Consumer Electron. 65(4): 506-515 (2019) - [j50]Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg, Chip-Hong Chang, Meng-Fan Chang, Yao-Wen Chang, Poki Chen, Pasquale Corsonello, Paolo Crovetti, Shiro Dosho, Rolf Drechsler, Ibrahim Abe M. Elfadel, Ruonan Han, Masanori Hashimoto, Chun-Huat Heng, Deukhyoun Heo, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Ajay Joshi, Rajiv V. Joshi, Tanay Karnik, Chulwoo Kim, Tony Tae-Hyoung Kim, Jaydeep Kulkarni, Volkan Kursun, Yoonmyung Lee, Hai Helen Li, Huawei Li, Prabhat Mishra, Baker Mohammad, Mehran Mozaffari Kermani, Makoto Nagata, Koji Nii, Partha Pratim Pande, Bipul C. Paul, Vasilis F. Pavlidis, José Pineda de Gyvez, Ioannis Savidis, Patrick Schaumont, Fabio Sebastiano, Anirban Sengupta, Mingoo Seok, Mircea R. Stan, Mark M. Tehranipoor, Aida Todri-Sanial, Marian Verhelst, Valerio Vignoli, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Jun Zhou, Mark Zwolinski, Stacey Weber:
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. IEEE Trans. Very Large Scale Integr. Syst. 27(2): 253-280 (2019) - [c55]Asmita Manna, Anirban Sengupta, Chandan Mazumdar:
A Quantitative Methodology for Business Process-Based Data Privacy Risk Computation. ACSS (2) 2019: 17-33 - [c54]Mahendra Rathor, Anirban Sengupta:
Enhanced Functional Obfuscation of DSP core using Flip-Flops and Combinational logic. ICCE-Berlin 2019: 1-5 - [c53]Anirban Sengupta, N. Prajwal Chandra, E. Ranjith Kumar:
Robust Digital Signature to Protect IP Core against Fraudulent Ownership and Cloning. ICCE-Berlin 2019: 1-3 - [c52]Anirban Sengupta, Gargi Gupta, Harshit Jalan:
Hardware Steganography for IP Core Protection of Fault Secured DSP Cores. ICCE-Berlin 2019: 1-6 - [c51]Anirban Sengupta, Utkarsh Kumar Singh, Piyush Kalkute Premchand:
Crypto based Multi-Variable Fingerprinting for Protecting DSP cores. ICCE-Berlin 2019: 1-6 - [c50]Anirban Sengupta:
Design Pruning of DSP Kernel for Multi Objective IP Core Architecture. ICCE 2019: 1-5 - [c49]Anirban Sengupta, Mahendra Rathor:
Improved Delay Estimation Model for Loop based DSP cores. ICCE 2019: 1-4 - [c48]Anirban Sengupta, Dipanjan Roy, Saraju P. Mohanty:
Low-Overhead Robust RTL Signature for DSP Core Protection: New Paradigm for Smart CE Design. ICCE 2019: 1-6 - [p1]Anirban Sengupta, Dipanjan Roy:
Low Cost Dual-Phase Watermark for Protecting CE Devices in IoT Framework. Security and Fault Tolerance in Internet of Things 2019: 21-41 - [e1]Anirban Sengupta, Sudeb Dasgupta, Virendra Singh, Rohit Sharma, Santosh Kumar Vishvakarma:
VLSI Design and Test - 23rd International Symposium, VDAT 2019, Indore, India, July 4-6, 2019, Revised Selected Papers. Communications in Computer and Information Science 1066, Springer 2019, ISBN 978-981-32-9766-1 [contents] - 2018
- [j49]Anirban Sengupta, Dipanjan Roy, Saraju P. Mohanty, Peter Corcoran:
A Framework for Hardware Efficient Reusable IP Core for Grayscale Image CODEC. IEEE Access 6: 871-882 (2018) - [j48]Anirban Sengupta, Dipanjan Roy:
Intellectual Property-Based Lossless Image Compression for Camera Systems [Hardware Matters]. IEEE Consumer Electron. Mag. 7(1): 119-124 (2018) - [j47]Deepak Kachave, Anirban Sengupta:
Shielding CE Hardware Against Reverse-Engineering Attacks Through Functional Locking [Hardware Matters]. IEEE Consumer Electron. Mag. 7(2): 111-114 (2018) - [j46]Dipanjan Roy, Anirban Sengupta:
Obfuscated JPEG Image Decompression IP Core for Protecting Against Reverse Engineering [Hardware Matter]. IEEE Consumer Electron. Mag. 7(3): 104-109 (2018) - [j45]Dipanjan Roy, Pallabi Sarkar, Anirban Sengupta, Mrinal Kanti Naskar:
Optimizing DSP Cores Using Design Transformation [Hardware Matters]. IEEE Consumer Electron. Mag. 7(4): 91-94 (2018) - [j44]Anirban Sengupta, Niranjan Kumar Ray:
Audio and Video Technologies: Recent Advances in Consumer Electronics. IEEE Consumer Electron. Mag. 7(5): 26 (2018) - [j43]Anirban Sengupta, Deepak Kachave:
Forensic engineering for resolving ownership problem of reusable IP core generated during high level synthesis. Future Gener. Comput. Syst. 80: 29-46 (2018) - [j42]Deepak Kachave, Anirban Sengupta, Shubha Neema, Panugothu Sri Harsha:
Effect of NBTI stress on DSP cores used in CE devices: threat model and performance estimation. IET Comput. Digit. Tech. 12(6): 268-278 (2018) - [j41]Anirban Sengupta, Deepak Kachave:
Spatial and Temporal Redundancy for Transient Fault-Tolerant Datapath. IEEE Trans. Aerosp. Electron. Syst. 54(3): 1168-1183 (2018) - [j40]Anirban Sengupta, Dipanjan Roy, Saraju P. Mohanty:
Triple-Phase Watermarking for Reusable IP Core Protection During Architecture Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(4): 742-755 (2018) - [j39]Anirban Sengupta, Saraju P. Mohanty, Fernando Pescador, Peter Corcoran:
Multi-Phase Obfuscation of Fault Secured DSP Designs With Enhanced Security Feature. IEEE Trans. Consumer Electron. 64(3): 356-364 (2018) - [j38]Anirban Sengupta, Dipanjan Roy, Saraju P. Mohanty, Peter Corcoran:
Low-Cost Obfuscated JPEG CODEC IP Core for Secure CE Hardware. IEEE Trans. Consumer Electron. 64(3): 365-374 (2018) - [c47]Anirban Sengupta, Dipanjan Roy:
Multi-phase watermark for IP core protection. ICCE 2018: 1-3 - [c46]Anirban Sengupta, Dipanjan Roy:
Reusable intellectual property core protection for both buyer and seller. ICCE 2018: 1-3 - [c45]Anirban Sengupta, Deepak Kachave:
Integrating Compiler Driven Transformation and Simulated Annealing Based Floorplan for Optimized Transient Fault Tolerant DSP Cores. iSES 2018: 17-20 - [c44]Anirban Sengupta, Saraju P. Mohanty:
Functional Obfuscation of DSP Cores Using Robust Logic Locking and Encryption. ISVLSI 2018: 709-713 - [c43]Anirban Sengupta, Shubha Neema, Pallabi Sarkar, Sri Harsha P, Saraju P. Mohanty, Mrinal Kanti Naskar:
Obfuscation of Fault Secured DSP Design Through Hybrid Transformation. ISVLSI 2018: 732-737 - 2017
- [j37]Anirban Sengupta, Dipanjan Roy:
Automated low cost scheduling driven watermarking methodology for modern CAD high-level synthesis tools. Adv. Eng. Softw. 110: 26-33 (2017) - [j36]Anirban Sengupta:
Hardware Security of CE Devices [Hardware Matters]. IEEE Consumer Electron. Mag. 6(1): 130-133 (2017) - [j35]Anirban Sengupta, Dipanjan Roy:
Antipiracy-Aware IP Chipset Design for CE Devices: A Robust Watermarking Approach [Hardware Matters]. IEEE Consumer Electron. Mag. 6(2): 118-124 (2017) - [j34]Saraju P. Mohanty, Anirban Sengupta, Parthasarathy Guturu, Elias Kougianos:
Everything You Want to Know About Watermarking: From Paper Marks to Hardware Protection: From paper marks to hardware protection. IEEE Consumer Electron. Mag. 6(3): 83-91 (2017) - [j33]Anirban Sengupta:
Hardware Vulnerabilities and Their Effects on CE Devices: Design for Security Against Trojans [Hardware Matters]. IEEE Consumer Electron. Mag. 6(3): 126-133 (2017) - [j32]Pallabi Sarkar, Anirban Sengupta, Santosh Rathlavat, Mrinal Kanti Naskar:
Designing Low-Cost Hardware Accelerators for CE Devices [Hardware Matters]. IEEE Consumer Electron. Mag. 6(4): 140-149 (2017) - [j31]Dipanjan Roy, Anirban Sengupta:
Low overhead symmetrical protection of reusable IP core using robust fingerprinting and watermarking during high level synthesis. Future Gener. Comput. Syst. 71: 89-101 (2017) - [j30]Anirban Sengupta, Saumya Bhadauria, Saraju P. Mohanty:
Low-cost security aware HLS methodology. IET Comput. Digit. Tech. 11(2): 68-79 (2017) - [j29]Anirban Sengupta, Dipanjan Roy, Saumya Bhadauria:
Low cost optimized Trojan secured schedule at behavioral level for single & Nested loop control data flow graphs (Invited Paper). Integr. 58: 378-389 (2017) - [j28]Anirban Sengupta, Deepak Kachave:
Low cost fault tolerance against kc-cycle and km-unit transient for loop based control data flow graphs during physically aware high level synthesis. Microelectron. Reliab. 74: 88-99 (2017) - [j27]Anirban Sengupta, Saumya Bhadauria, Saraju P. Mohanty:
TL-HLS: Methodology for Low Cost Hardware Trojan Security Aware Scheduling With Optimal Loop Unrolling Factor During High Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(4): 655-668 (2017) - [j26]Anirban Sengupta, Dipanjan Roy, Saraju P. Mohanty, Peter Corcoran:
DSP design protection in CE through algorithmic transformation based structural obfuscation. IEEE Trans. Consumer Electron. 63(4): 467-476 (2017) - [j25]Anirban Sengupta, Sandip Kundu:
Guest Editorial Securing IoT Hardware: Threat Models and Reliable, Low-Power Design Solutions. IEEE Trans. Very Large Scale Integr. Syst. 25(12): 3265-3267 (2017) - [c42]Srijita Basu, Anirban Sengupta, Chandan Mazumdar:
A Quantitative Methodology for Cloud Security Risk Assessment. CLOSER 2017: 92-103 - [c41]Anirban Sengupta, Deepak Kachave, Shubha Neema, Panugothu Sri Harsha:
Reliability and Threat Analysis of NBTI Stress on DSP Cores. iNIS 2017: 11-14 - [c40]Pallabi Sarkar, Anirban Sengupta, Santosh Rathlavat, Mrinal Kanti Naskar:
A Firefly Algorithm Driven Approach for High Level Synthesis. iNIS 2017: 15-19 - [c39]Anirban Sengupta, Dipanjan Roy:
Mathematical Validation of HWT Based Lossless Image Compression. iNIS 2017: 20-22 - [c38]Vipul Kumar Mishra, Anirban Sengupta:
Comprehensive Operation Chaining Based Schedule Delay Estimation During High Level Synthesis. iNIS 2017: 66-68 - 2016
- [j24]Anirban Sengupta, Saumya Bhadauria:
Exploring Low Cost Optimal Watermark for Reusable IP Cores During High Level Synthesis. IEEE Access 4: 2198-2215 (2016) - [j23]Anirban Sengupta, Saraju P. Mohanty, Fabrizio Lombardi, Mark Zwolinski:
IEEE Access Special Section Editorial: Security and Reliability Aware System Design for Mobile Computing Devices. IEEE Access 4: 2976-2980 (2016) - [j22]Anirban Sengupta:
Intellectual Property Cores: Protection designs for CE products. IEEE Consumer Electron. Mag. 5(1): 83-88 (2016) - [j21]Anirban Sengupta:
Design Flow of a Digital IC: The role of digital IC/SOC design in CE products. IEEE Consumer Electron. Mag. 5(2): 58-62 (2016) - [j20]Anirban Sengupta:
Evolution of the IP Design Process in the Semiconductor/EDA Industry Hardware Matters. IEEE Consumer Electron. Mag. 5(2): 123-126 (2016) - [j19]Anirban Sengupta:
Cognizance on Intellectual Property: A High-Level Perspective [Hardware Matters]. IEEE Consumer Electron. Mag. 5(3): 126-128 (2016) - [j18]Anirban Sengupta:
Soft IP Core Design Resiliency Against Terrestrial Transient Faults for CE Products [Hardware Matters]. IEEE Consumer Electron. Mag. 5(4): 129-131 (2016) - [j17]Srijita Basu, Anirban Sengupta, Chandan Mazumdar:
Modelling operations and security of cloud systems using Z-notation and Chinese Wall security policy. Enterp. Inf. Syst. 10(9): 1024-1046 (2016) - [j16]Deepak Kachave, Anirban Sengupta:
Integrating physical level design and high level synthesis for simultaneous multi-cycle transient and multiple transient fault resiliency of application specific datapath processors. Microelectron. Reliab. 60: 141-152 (2016) - [c37]Jaya Bhattacharjee, Anirban Sengupta, Chandan Mazumdar:
A Quantitative Methodology for Security Risk Assessment of Enterprise Business Processes. ICISSP 2016: 388-399 - [c36]Anirban Sengupta, Saumya Bhadauria, Saraju P. Mohanty:
Embedding low cost optimal watermark during high level synthesis for reusable IP core protection. ISCAS 2016: 974-977 - [c35]Deepak Kachave, Anirban Sengupta:
Protecting Ownership of Reusable IP Core Generated during High Level Synthesis. iNIS 2016: 80-82 - [c34]Anirban Sengupta, Deepak Kachave:
Generating Multi-cycle and Multiple Transient Fault Resilient Design During Physically Aware High Level Synthesis. ISVLSI 2016: 75-80 - [c33]Srijita Basu, Anirban Sengupta, Chandan Mazumdar:
An Automated Methodology for Secured User Allocation in Cloud. SSCC 2016: 137-151 - 2015
- [j15]Anirban Sengupta, Saumya Bhadauria:
Automated design space exploration of multi-cycle transient fault detectable datapath based on multi-objective user constraints for application specific computing. Adv. Eng. Softw. 82: 14-24 (2015) - [j14]Saumya Bhadauria, Anirban Sengupta:
Adaptive bacterial foraging driven datapath optimization: Exploring power-performance tradeoff in high level synthesis. Appl. Math. Comput. 269: 265-278 (2015) - [j13]Anirban Sengupta, Saumya Bhadauria:
Bacterial foraging driven exploration of multi cycle fault tolerant datapath based on power-performance tradeoff in high level synthesis. Expert Syst. Appl. 42(10): 4719-4732 (2015) - [j12]Anirban Sengupta, Vipul Kumar Mishra:
Simultaneous exploration of optimal datapath and loop based high level transformation during area-delay tradeoff in architectural synthesis using swarm intelligence. Int. J. Knowl. Based Intell. Eng. Syst. 19(1): 47-61 (2015) - [j11]Anirban Sengupta, Reza Sedaghat:
Swarm intelligence driven design space exploration of optimal k-cycle transient fault secured datapath during high level synthesis based on user power-delay budget. Microelectron. Reliab. 55(6): 990-1004 (2015) - [c32]Anirban Sengupta, Reza Sedaghat:
Exploration of optimal multi-cycle transient fault secured datapath during high level synthesis based on user area-delay budget. CCECE 2015: 69-74 - [c31]Pallabi Sarkar, Anirban Sengupta, Mrinal Kanti Naskar:
GA driven integrated exploration of loop unrolling factor and datapath for optimal scheduling of CDFGs during high level synthesis. CCECE 2015: 75-80 - [c30]Anirban Sengupta, Saumya Bhadauria:
Untrusted Third Party Digital IP Cores: Power-Delay Trade-off Driven Exploration of Hardware Trojan Secured Datapath during High Level Synthesis. ACM Great Lakes Symposium on VLSI 2015: 167-172 - [c29]Anirban Sengupta, Saumya Bhadauria:
Secure Information Processing during System-Level: Exploration of an Optimized Trojan Secured Datapath for CDFGs during HLS Based on User Constraints. iNIS 2015: 1-6 - [c28]Anirban Sengupta, Saumya Bhadauria:
User power-delay budget driven PSO based design space exploration of optimal k-cycle transient fault secured datapath during high level synthesis. ISQED 2015: 289-292 - [c27]Anirban Sengupta:
Modeling Dependencies of ISO/IEC 27002: 2013 Security Controls. SSCC 2015: 354-367 - [c26]Anirban Sengupta, Saumya Bhadauria:
Automated design space exploration of transient fault detectable datapath based on user specified power and delay constraints. VLSI-DAT 2015: 1-4 - 2014
- [j10]Vipul Kumar Mishra, Anirban Sengupta:
MO-PSE: Adaptive multi-objective particle swarm optimization based design space exploration in architectural synthesis for application specific processor design. Adv. Eng. Softw. 67: 111-124 (2014) - [j9]Jaya Bhattacharjee, Anirban Sengupta, Chandan Mazumdar, Mridul Sankar Barik:
A two-phase quantitative methodology for enterprise information security risk analysis. Comput. Syst. Sci. Eng. 29(1) (2014) - [j8]Anirban Sengupta, Vipul Kumar Mishra:
Automated exploration of datapath and unrolling factor during power-performance tradeoff in architectural synthesis using multi-dimensional PSO algorithm. Expert Syst. Appl. 41(10): 4691-4703 (2014) - [c25]Anirban Sengupta, Saumya Bhadauria:
Automated exploration of datapath in high level synthesis using temperature dependent bacterial foraging optimization algorithm. CCECE 2014: 1-5 - [c24]Anirban Sengupta, Vipul Kumar Mishra:
Automated parallel exploration of datapath and Unrolling Factor in High Level Synthesis using hyper-dimensional particle swarm encoding. CCECE 2014: 1-5 - [c23]Anirban Sengupta, Vipul Kumar Mishra:
Time Varying vs. Fixed Acceleration Coefficient PSO Driven Exploration during High Level Synthesis: Performance and Quality Assessment. ICIT 2014: 281-286 - [c22]Anirban Sengupta, Saumya Bhadauria:
Error Masking of Transient Faults: Exploration of a Fault Tolerant Datapath Based on User Specified Power and Delay Budget. ICIT 2014: 345-350 - [c21]Jaya Bhattacharjee, Anirban Sengupta, Chandan Mazumdar:
A Formal Methodology for Modeling Threats to Enterprise Assets. ICISS 2014: 149-166 - [c20]Vipul Kumar Mishra, Anirban Sengupta:
PSDSE: Particle Swarm Driven Design Space Exploration of Architecture and Unrolling Factors for Nested Loops in High Level Synthesis. ISED 2014: 10-14 - [c19]Anirban Sengupta, Vipul Kumar Mishra:
Integrated particle swarm optimization (i-PSO): An adaptive design space exploration framework for power-performance tradeoff in architectural synthesis. ISQED 2014: 60-67 - [c18]Anirban Sengupta, Vipul Kumar Mishra:
Swarm Intelligence Driven Simultaneous Adaptive Exploration of Datapath and Loop Unrolling Factor during Area-Performance Tradeoff. ISVLSI 2014: 106-111 - [c17]Anirban Sengupta, Saumya Bhadauria:
Exploration of Multi-objective Tradeoff during High Level Synthesis Using Bacterial Chemotaxis and Dispersal. KES 2014: 63-72 - 2013
- [c16]Jaya Bhattacharjee, Anirban Sengupta, Chandan Mazumdar:
A formal methodology for Enterprise Information Security risk assessment. CRiSIS 2013: 1-9 - [c15]Anirban Sengupta:
A methodology for self correction scheme based fast multi criterion exploration and architectual synthesis of data dominated applications. ICACCI 2013: 430-436 - [c14]Anirban Sengupta, Vipul Kumar Mishra:
D-logic exploration: Rapid search of Pareto fronts during architectural synthesis of custom processors. ICACCI 2013: 586-593 - 2012
- [j7]Anirban Sengupta, Reza Sedaghat, Pallabi Sarkar:
Rapid exploration of integrated scheduling and module selection in high level synthesis for application specific processor design. Microprocess. Microsystems 36(4): 303-314 (2012) - [j6]Anirban Sengupta, Reza Sedaghat, Pallabi Sarkar:
A multi structure genetic algorithm for integrated design space exploration of scheduling and allocation in high level synthesis for DSP kernels. Swarm Evol. Comput. 7: 35-46 (2012) - [c13]Anirban Sengupta, Chandan Mazumdar, Aditya Bagchi:
Specification and validation of enterprise information security policies. CUBE 2012: 801-808 - [c12]Jaya Bhattacharjee, Anirban Sengupta, Chandan Mazumdar, Mridul Sankar Barik:
A two-phase quantitative methodology for enterprise information security risk analysis. CUBE 2012: 809-815 - 2011
- [j5]Anirban Sengupta, Chandan Mazumdar:
A Mark-Up Language for the Specification of Information Security Governance Requirements. Int. J. Inf. Secur. Priv. 5(2): 33-53 (2011) - [j4]Anirban Sengupta, Chandan Mazumdar, Aditya Bagchi:
A Formal Methodology for Detecting Managerial Vulnerabilities and Threats in an Enterprise Information System. J. Netw. Syst. Manag. 19(3): 319-342 (2011) - [j3]Anirban Sengupta, Reza Sedaghat, Zhipeng Zeng:
Multi-objective efficient design space exploration and architectural synthesis of an application specific processor (ASP). Microprocess. Microsystems 35(4): 392-404 (2011) - [j2]Anirban Sengupta, Reza Sedaghat, Zhipeng Zeng:
Rapid design space exploration by hybrid fuzzy search approach for optimal architecture determination of multi objective computing systems. Microelectron. Reliab. 51(2): 502-512 (2011) - [c11]Anirban Sengupta, Reza Sedaghat, Pallabi Sarkar:
Integrated design space exploration based on power-performance trade-off using genetic algorithm. ACAI 2011: 77-81 - [c10]Pallabi Sarkar, Reza Sedaghat, Anirban Sengupta:
Application specific processor vs. microblaze soft core RISC processor: FPGA based performance and CPR analysis. ACAI 2011: 82-85 - [c9]Anirban Sengupta, Reza Sedaghat, Pallabi Sarkar, Summit Sehgal:
Integrated scheduling, allocation and binding in High Level Synthesis for performance-area tradeoff of digital media applications. CCECE 2011: 533-537 - [c8]Anirban Sengupta, Reza Sedaghat, Pallabi Sarkar, Summit Sehgal:
Priority function based power efficient rapid Design Space Exploration of scheduling and module selection in high level synthesis. CCECE 2011: 538-543 - [c7]Sulagna Bandopadhyay, Anirban Sengupta, Chandan Mazumdar:
A quantitative methodology for information security control gap analysis. ICCCS 2011: 537-540 - [c6]Anirban Sengupta, Reza Sedaghat:
Integrated scheduling, allocation and binding in High Level Synthesis using multi structure genetic algorithm based design space exploration. ISQED 2011: 486-494 - 2010
- [j1]Anirban Sengupta, Reza Sedaghat, Zhipeng Zeng:
A high level synthesis design flow with a novel approach for efficient design space exploration in case of multi-parametric optimization objective. Microelectron. Reliab. 50(3): 424-437 (2010) - [c5]Anirban Sengupta, Reza Sedaghat, Zhipeng Zeng:
Rapid design space exploration for multi parametric optimization of VLSI designs. ISCAS 2010: 3164-3167 - [c4]Zhipeng Zeng, Reza Sedaghat, Anirban Sengupta:
A framework for fast design space exploration using fuzzy search for VLSI computing Architectures. ISCAS 2010: 3176-3179
2000 – 2009
- 2009
- [c3]Anirban Sengupta, Chandan Mazumdar, Aditya Bagchi:
A formal methodology for detection of vulnerabilities in an enterprise information system. CRiSIS 2009: 74-81 - 2006
- [c2]Anirban Sengupta, Mridul Sankar Barik:
Towards a Formal Specification Method for Enterprise Information System Security. ICISS 2006: 373-376 - 2005
- [c1]Anirban Sengupta, Aniruddha Mukhopadhyay, Koel Ray, Aveek Guha Roy, Dipankar Aich, Mridul Sankar Barik, Chandan Mazumdar:
A Web-Enabled Enterprise Security Management Framework Based on a Unified Model of Enterprise Information System Security . ICISS 2005: 328-331
Coauthor Index
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