default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID23rd VDAT 2019: Indore, India
- Anirban Sengupta, Sudeb Dasgupta, Virendra Singh, Rohit Sharma, Santosh Kumar Vishvakarma:
VLSI Design and Test - 23rd International Symposium, VDAT 2019, Indore, India, July 4-6, 2019, Revised Selected Papers. Communications in Computer and Information Science 1066, Springer 2019, ISBN 978-981-32-9766-1
Analog and Mixed Signal Design
- Varun Kumar Dwivedi, Madhvi Sharma, Chandaka Venu:
Automations and Methodologies for Efficient and Quality Conscious Analog Layout Implementation. 3-13 - Archana Sunitha, Bhaskar Manickam
:
A 2.4 GHz High Efficiency Capacitive Cross Coupled Common Gate Class-E Differential Power Amplifier. 14-22 - Javed S. Gaggatur, Abhishek Chaturvedi:
A 1.25-20 GHz Wide Tuning Range Frequency Synthesis for 40-Gb/s SerDes Application. 23-35 - Bandan Kumar Bhoi, Neeraj Kumar Misra, Shailesh Singh Chouhan, Sarthak Acharya:
Analyzing Design Parameters of Nano-Magnetic Technology Based Converter Circuit. 36-46 - Debanjana Datta, Sweta Agarwal, Vikash Kumar, Mayank Raj, Baidyanath Ray, Ayan Banerjee:
Design of Current Mode Sigmoid Function and Hyperbolic Tangent Function. 47-60 - M. Mohamed Asan Basiri:
Flexible Adaptive FIR Filter Designs Using LMS Algorithm. 61-71 - Chandan Das, Sarit Chakraborty, Susanta Chakraborty:
An Efficient Test and Fault Tolerance Technique for Paper-Based DMFB. 72-86 - Amartya Dutta, Riya Majumder, Debasis Dhal, Rajat Kumar Pal:
A Generalized Technique of Automated Pin Sharing on Hexagonal Electrode Based Digital Microfluidic Biochip Along with Its Design Methodology. 87-101 - Jyotiranjan Swain, Rajesh Kolluri, Sumanta Pyne:
A Space Efficient Greedy Droplet Routing for Digital Microfluidics Biochip. 102-114 - Aditya Kumar Hota, Kabiraj Sethi:
Design of 635 MHz Bandpass Filter Using High-Q Floating Active Inductor. 115-125 - Saroja V. Siddamal, Suhas B. Shirol, Shraddha Hiremath, Nalini C. Iyer:
Design and Physical Implementation of Mixed Signal Elapsed Time Counter in 0.18 µm CMOS Technology. 126-140 - M. Mahendra Reddy, Sounak Roy:
Clock Pulse Based Foreground Calibration of a Sub-Radix-2 Successive Approximation Register ADC. 141-149 - Moumita Acharya, Samik Basu, Biranchi Narayan Behera, Amlan Chakrabarti:
Approximate Computing Based Adder Design for DWT Application. 150-163 - Purvi Agrawal, Ruchi Dhamnani, Ananya Garg, Shrivishal Tripathi, Manoj Kumar Majumder:
An Efficient Wireless Charging Technique Using Inductive and Resonant Circuits. 164-170 - Swatilekha Majumdar:
A Novel Gate-Level On-Chip Crosstalk Noise Reduction Circuit for Deep Sub-micron Technology. 171-179 - Arun Mohan, Saroj Mondal, Surya Shankar Dan:
On-Chip Threshold Compensated Voltage Doubler for RF Energy Harvesting. 180-189 - Ambika Prasad Shah, Amirhossein Moshrefi, Michael Waltl:
Utilizing NBTI for Operation Detection of Integrated Circuits. 190-201 - Raviteja Kammari, Vijaya Sankara Rao Pasupureddi:
A Widely Linear, Power Efficient, Charge Controlled Delay Element for Multi-phase Clock Generation in 1.2 V, 65 nm CMOS. 202-214 - Sunanda Ambulker, Jitendra Kumar Mishra, Sangeeta Nakhate:
A CMOS Low Noise Amplifier with Improved Gain. 215-223 - Avinash Verma, Gaurav Kaushal:
Radiation Hardened by Design Sense Amplifier. 224-235 - Sayantani Roy, Arighna Deb, Debesh K. Das:
Delay Efficient All Optical Carry Lookahead Adder. 236-244
Computing Architecture and Security
- M. Mohamed Asan Basiri:
Asynchronous Hardware Design for Floating Point Multiply-Accumulate Circuit. 247-257 - Saurabh Gangurde, Binod Kumar:
A Unified Methodology for Hardware Obfuscation and IP Watermarking. 258-271 - S. Shanthi Rekha, P. Saravanan:
Threshold Implementation of a Low-Cost CLEFIA-128 Cipher for Power Analysis Attack Resistance. 272-285 - Devika R. Nair, A. Purushothaman:
Brain Inspired One Shot Learning Method for HD Computing. 286-297 - Sajid Khan, Neha Gupta, Abhinav Vishwakarma, Shailesh Singh Chouhan, Jai Gopal Pandey, Santosh Kumar Vishvakarma:
Dual-Edge Triggered Lightweight Implementation of AES for IoT Security. 298-307 - Rose George Kunthara, K. Neethu, Rekha K. James, Simi Zerine Sleeba, Tripti S. Warrier, John Jose:
2L-2D Routing for Buffered Mesh Network-on-Chip. 308-320 - Gopal Raut, Vishal Bhartiy, Gunjan Rajput, Sajid Khan, Ankur Beohar, Santosh Kumar Vishvakarma:
Efficient Low-Precision CORDIC Algorithm for Hardware Implementation of Artificial Neural Network. 321-333 - Sajid Khan, Neha Gupta, Gopal Raut, Gunjan Rajput, Jai Gopal Pandey, Santosh Kumar Vishvakarma:
An Ultra Low Power AES Architecture for IoT. 334-344 - Rajul Bansal, Abhijit Karmakar:
Efficient Closely-Coupled Integration of AES Coprocessor with LEON3 Processor. 345-356 - Shah Zahid Yousuf, Anil Kumar Bhardwaj, Rohit Sharma:
Investigating the Role of Parasitic Resistance in a Class of Nanoscale Interconnects. 357-370 - Priyamvada Sharma, Bishnu Prasad Das:
A True Single-Phase Error Masking Flip-Flop with Reduced Clock Power for Near-Threshold Designs. 371-382
Hardware Design and Optimization
- K. P. Raghunath, K. V. Manu Sagar, T. Gokulan, Kundan Kumar, Chetan Singh Thakur:
ASIC Based LVDT Signal Conditioner for High-Accuracy Measurements. 385-397 - Neelam Arya, Anil Kumar Rajput, Manisha Pattanaik, G. K. Sharma:
Quality Driven Energy Aware Approximated Core Transform Architecture for HEVC Standard. 398-412 - V. S. Vineesh, Binod Kumar, Jay Adhaduk:
Identification of Effective Guidance Hints for Better Design Debugging by Formal Methods. 413-427 - Piyush Tankwal, Vikas Nehra, Brajesh Kumar Kaushik:
Comparative Analysis of Logic Gates Based on Spin Transfer Torque (STT) and Differential Spin Hall Effect (DSHE) Switching Mechanisms. 428-441 - P. Veda Bhanu, Pranav Venkatesh Kulkarni, Sai Pranavi Avadhanam, Soumya J., Linga Reddy Cenkeramaddi:
Multi-application Based Fault-Tolerant Network-on-Chip Design for Mesh Topology Using Reconfigurable Architecture. 442-454 - Mrinal Goswami, Mayukh Roy Choudhury, Bibhash Sen:
A Realistic Configurable Level Triggered Flip-Flop in Quantum-Dot Cellular Automata. 455-467 - Priyanka Panigrahi, Rajesh Kumar Jha, Chandan Karfa:
User Guided Register Manipulation in Digital Circuits. 468-481 - Aneesh Raveendran, Sandra Jean, J. Mervin, Vivian Desalphine, A. David Selvakumar:
RISC-V Half Precision Floating Point Instruction Set Extensions and Co-processor. 482-495 - Aneesh Raveendran, Vinay Kumar, Vivian Desalphine, David Selvakumar:
Functional Simulation Verification of RISC-V Instruction Set Based High Level Language Modeled FPU. 496-509 - Govind Bajpai, Aniket Gupta, Nitanshu Chauhan:
Real Time Implementation of Convolutional Neural Network to Detect Plant Diseases Using Internet of Things. 510-522 - Anushka Singh, Yash Sharma, Arvind Sharma, Archana Pandey:
A Novel 20nm FinFET Based 10T SRAM Cell Design for Improved Performance. 523-531 - Muneeb Sulthan, Shubhajit Roy Chowdury, Rajnish Garg, Alok Tripathi:
Design of a Power Efficient Pulse Latch Circuit as a Solution for Master Slave Flip-Flop. 532-540 - Kamini Singh, R. S. Gamad, P. P. Bansod:
Design and Analysis for Power Reduction with High SNM of 10T SRAM Cell. 541-549
Low Power VLSI and Memory Design
- Kanika Monga, Nitin Chaturvedi:
A CMOS/MTJ Based Novel Non-volatile SRAM Cell with Asynchronous Write Termination for Normally OFF Applications. 553-564 - Deepthi Amuru, Andleeb Zahra, Zia Abbas:
Statistical Variation Aware Leakage and Total Power Estimation of 16 nm VLSI Digital Circuits Based on Regression Models. 565-578 - Victor Jeffry Louis, Jai Gopal Pandey:
A Novel Design of SRAM Using Memristors at 45 nm Technology. 579-589 - Yadukrishnan Mekkattillam, Satyajit Mohapatra, Nihar R. Mohapatra:
Design and Calibration of 14-bit 10 KS/s Low Power SAR ADC for Bio-medical Applications. 590-604 - Bappaditya Mondal, Anirban Bhattacharjee, Subham Saha, Shalini Parekh, Chandan Bandyopadhyay, Hafizur Rahaman:
An Approach for Detection of Node Displacement Fault (NDF) in Reversible Circuit. 605-616 - Vijay Rao Kumbhare, Punya Prasanna Paltani, Manoj Kumar Majumder:
Novel Approach for Improved Signal Integrity and Power Dissipation Using MLGNR Interconnects. 617-629 - Neha Gupta, Jitesh Prasad, Rana Sagar Kumar, Gunjan Rajput, Santosh Kumar Vishvakarma:
A Robust Low-Power Write-Assist Data-Dependent-Power-Supplied 12T SRAM Cell. 630-642 - Neha Gupta, Tanisha Gupta, Sajid Khan, Abhinav Vishwakarma, Santosh Kumar Vishvakarma:
Low Leakage Highly Stable Robust Ultra Low Power 8T SRAM Cell. 643-654 - Ankur Beohar, Gopal Raut, Gunjan Rajput, Abhinav Vishwakarma, Ambika Prasad Shah, Bhupendra Singh Reniwal, Santosh Kumar Vishvakarma:
Compact Spiking Neural Network System with SiGe Based Cylindrical Tunneling Transistor for Low Power Applications. 655-663
Device Modelling
- Shivendra Singh Parihar, Ramchandra Gurjar:
Compact Modeling of Drain-Extended MOS Transistor Using BSIM-BULK Model. 667-678 - Harshil Goyal, Vishwani D. Agrawal:
Technology Characterization Model and Scaling for Energy Management. 679-693 - Shivendra Yadav, Chithraja Rajan, Dheeraj Sharma, Sanjay Balotiya:
GaAs-SiGe Based Novel Device Structure of Doping Less Tunnel FET. 694-701 - Nirmal Kumar Boran, Dinesh Kumar Yadav, Rishabh R. Iyer:
Performance Modelling and Dynamic Scheduling on Heterogeneous-ISA Multi-core Architectures. 702-715 - Venkata Appa Rao Yempada, Srivatsava Jandhyala:
Simulation Study of III-V Lateral Tunnel FETs with Gate-Drain Underlap. 716-726 - Shagun Pal, Brijesh Kumar:
Low-Voltage Dual-Gate Organic Thin Film Transistors with Distinctly Placed Source and Drain. 727-738
Hardware Implementation
- Sistla Lakshmi Manasa, G. Lakshmi Narayanan:
A Latency and Throughput Efficient Successive Cancellation Decoding of Polar Codes. 741-748 - Ankur Pokhara, Biswajit Mishra, Purvi Patel:
All-Digital CMOS On-Chip Temperature Sensor with Time-Assisted Analytical Model. 749-763 - Anam Sabir, Anushree Jain, Yashwini Nathwani, Vaibhav Neema:
Intelligent Traffic Light Controller: A Solution for Smart City Traffic Problem. 764-772
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-11-20 21:05 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
