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ORCIDP. Saravanan 0001
Person information
- affiliation: PSG College of Technology, Department of Electronics and Communication Engineering, Coimbatore, Tamil Nadu, India
Other persons with the same name
- P. Saravanan — disambiguation page
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2020 – today
- 2024
[j13]Mohammad Abdussami, Sanjeev Kumar Dwivedi, Taher Al-Shehari, P. Saravanan, Mohammed Kadrie, Taha Alfakih, Hussain Alsalman, Ruhul Amin
:
DEAC-IoT: Design of lightweight authenticated key agreement protocol for Intra and Inter-IoT device communication using ECC with FPGA implementation. Comput. Electr. Eng. 120: 109696 (2024)- [j12]Priyadharshini Mohanraj, Saravanan Paramasivam:
A Multiobjective Approach for Side-Channel Based Hardware Trojan Detection Using Power Traces. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 107(5): 825-835 (2024) - [j11]S. Mugunthan, Venkatasamy Sureshkumar, Saravanan Paramasivam, Ruhul Amin:
VAuth: Robust Lightweight Mutual Authentication Protocol Preserving User's Anonymity for VANET With FPGA Implementation. IEEE Trans. Intell. Transp. Syst. 25(12): 21097-21106 (2024) - [j10]R. Parthasarathy, P. Saravanan:
Low Cost Implementation of Authenticated Encryption Using Spongift. Wirel. Pers. Commun. 136(4): 2479-2493 (2024) - [c9]Priyadharshini Mohanraj, Saravanan Paramasivam, Charukesh V., Nihar Ahamed Fathima A.:
A Hardware Trojan Detection Method for Gate-Level Netlists Employing the CAMELOT Measure. ICDCS 2024: 183-187 - [c8]P. Saravanan, Harreni V, Krishnaveni V:
Three Stage Operational Amplifier with Split Length Differential Input Pair for IoT Applications. VDAT 2024: 1-6 - 2023
- [j9]Saravanan Paramasivam, J. Jenitha, S. Sanjana, Majid Haghparast:
Compact Quantum Circuit Design of PUFFIN and PRINT Lightweight Ciphers for Quantum Key Recovery Attack. IEEE Access 11: 66767-66776 (2023) - [j8]Mohammad Abdussami, Ruhul Amin, P. Saravanan, Satyanarayana Vollala:
BSAPM: BlockChain based secured authentication protocol for large scale WSN with FPGA implementation. Comput. Commun. 209: 63-77 (2023) - 2022
- [j7]Venkatasamy Sureshkumar, P. Chinnaraj, P. Saravanan, Ruhul Amin, Joel J. P. C. Rodrigues:
Authenticated Key Agreement Protocol for Secure Communication Establishment in Vehicle-to-Grid Environment With FPGA Implementation. IEEE Trans. Veh. Technol. 71(4): 3470-3479 (2022) - 2021
- [j6]P. Saravanan, Shanthi Rekha Shanmugham:
Time-shared AES-128 implementation with extremely low-cost for smart card applications. Int. J. Inf. Comput. Secur. 16(3/4): 239-254 (2021) - [c7]P. Saravanan, J. Jenitha, S. R. Aasish, S. Sanjana:
Quantum Circuit Design of RECTANGLE Lightweight Cipher. VDAT 2021: 1-4 - [c6]P. Saravanan, B. Syndia Priyadarshini, P. Vignesh Kanna, P. Vaishnavi:
Hardware Accelerator for Dual Standard Deblocking Filter. VLSID 2021: 210-215
2010 – 2019
- 2019
- [j5]Shanthi Rekha Shanmugham, P. Saravanan:
Low-Cost AES-128 Implementation for Edge Devices in IoT Applications. J. Circuits Syst. Comput. 28(4): 1950062:1-1950062:24 (2019) - [c5]S. Shanthi Rekha, P. Saravanan:
Threshold Implementation of a Low-Cost CLEFIA-128 Cipher for Power Analysis Attack Resistance. VDAT 2019: 272-285 - 2018
- [j4]Shanthi Rekha Shanmugham, Saravanan Paramasivam:
Survey on power analysis attacks and its impact on intelligent sensor networks. IET Wirel. Sens. Syst. 8(6): 295-304 (2018) - [j3]P. Saravanan, P. Kalpana:
Novel Reversible Design of Advanced Encryption Standard Cryptographic Algorithm for Wireless Sensor Networks. Wirel. Pers. Commun. 100(4): 1427-1458 (2018) - [c4]P. Saravanan, Babu M. Mehtre:
A Novel Approach to Detect Hardware Malware Using Hamming Weight Model and One Class Support Vector Machine. VDAT 2018: 159-172 - 2017
- [c3]Shanthi Rekha Shanmugham, P. Saravanan:
Low Cost Circuit Level Implementation of PRESENT-80 S-BOX. VDAT 2017: 354-362 - 2015
- [j2]P. Saravanan, P. Kalpana:
Performance Analysis of Reversible Finite Field Arithmetic Architectures Over GF(p) and GF(2m) in Elliptic Curve Cryptography. J. Circuits Syst. Comput. 24(8): 1550122:1-1550122:28 (2015) - 2014
- [j1]P. Saravanan, P. Kalpana:
Energy Efficient Reversible Building Blocks Resistant to Power Analysis Attacks. J. Circuits Syst. Comput. 23(9) (2014) - [c2]P. Saravanan, P. Kalpana, V. Prcethisri, V. Sneha:
Power analysis attack using neural networks with wavelet transform as pre-processor. VDAT 2014: 1-6 - 2012
- [c1]P. Saravanan, P. Chandrasekar, Livya Chandran, Nikilla Sriram, P. Kalpana:
Design and Implementation of Efficient Vedic Multiplier Using Reversible Logic. VDAT 2012: 364-366
Coauthor Index
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