"Design and Physical Implementation of Mixed Signal Elapsed Time Counter in ..."

Saroja V. Siddamal et al. (2019)

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DOI: 10.1007/978-981-32-9767-8_11

access: closed

type: Conference or Workshop Paper

metadata version: 2022-06-23

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  dblp key:
  - conf/vdat/SiddamalSHI19
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  - https://dblp.org/rec/conf/vdat/SiddamalSHI19
Saroja V. Siddamal, Suhas B. Shirol, Shraddha Hiremath, Nalini C. Iyer:
Design and Physical Implementation of Mixed Signal Elapsed Time Counter in 0.18 µm CMOS Technology. VDAT 2019: 126-140

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