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ORCIDBehavioral Synthesis for Hardware Security, 2022
- Srinivas Katkoori
, Sheikh Ariful Islam:
Behavioral Synthesis for Hardware Security. Springer International Publishing 2022, ISBN 978-3-030-78840-7 - Srinivas Katkoori, Sheikh Ariful Islam:
Introduction and Background. 1-14 - Sheikh Ariful Islam, Srinivas Katkoori:
Behavioral Synthesis of Key-Obfuscated RTL IP. 17-42 - Nandeesha Veeranna, Benjamin Carrion Schafer:
Source Code Obfuscation of Behavioral IPs: Challenges and Solutions. 43-56 - Pranesh Santikellur, Rajat Subhra Chakraborty, Swarup Bhunia:
Hardware IP Protection Using Register Transfer Level Locking and Obfuscation of Control and Data Flow. 57-69 - Hannah Badier, Jean-Christophe Le Lann, Philippe Coussy, Guy Gogniat:
Protecting Behavioral IPs During Design Time: Key-Based Obfuscation Techniques for HLS in the Cloud. 71-93 - Christian Pilato, Donatella Sciuto, Francesco Regazzoni, Siddharth Garg, Ramesh Karri:
Protecting Hardware IP Cores During High-Level Synthesis. 95-115 - Anirban Sengupta, Mahendra Rathor:
Hardware (IP) Watermarking During Behavioral Synthesis. 119-145 - Richa Agrawal, Ranga Vemuri:
Encoding of Finite-State Controllers for Graded Security and Power. 147-175 - Matthew Lewandowski, Srinivas Katkoori:
State Encoding Based Watermarking of Sequential Circuits Using Hybridized Darwinian Genetic Algorithm. 177-202 - Sheikh Ariful Islam, Srinivas Katkoori:
Hardware Trojan Localization: Modeling and Empirical Approach. 205-231 - Chen Liu, Chengmo Yang:
Defense Against Hardware Trojan Collusion in MPSoCs. 233-264 - Farhath Zareen, Robert Karam:
A Framework for Detecting Hardware Trojans in RTL Using Artificial Immune Systems. 265-287 - S. T. Choden Konigsmark, Wei Ren, Martin D. F. Wong, Deming Chen:
High-Level Synthesis for Minimizing Power Side-Channel Information Leakage. 291-317 - Mike Borowczak, Ranga Vemuri:
S*FSMs for Reduced Information Leakage: Power Side Channel Protection Through Secure Encoding. 319-342 - Steffen Peter, Tony Givargis:
Generation and Verification of Timing Attack Resilient Schedules During the High-Level Synthesis of Integrated Circuits. 343-363 - Wei Hu, Armaiti Ardeshiricham, Lingjuan Wu, Ryan Kastner:
Integrating Information Flow Tracking into High-Level Synthesis Design Flow. 365-387
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last updated on 2025-01-26 23:49 CET by the dblp team
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