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2020 – today
- 2023
[c10]Nameshwari Verma, Pallabi Sarkar
:
System Complexity Reduction Using 3-D Matrices and Novel Logic Gates. ICCCNT 2023: 1-5- 2020
- [c9]Mahendra Rathor, Pallabi Sarkar, Vipul Kumar Mishra, Anirban Sengupta:
Securing IP Cores in CE Systems using Key-driven Hash-chaining based Steganography. ICCE-Berlin 2020: 1-4
2010 – 2019
- 2019
- [j5]Pallabi Sarkar, Dipanjan Roy, Anirban Sengupta, Mrinal Kanti Naskar:
Signature-Free Watermark for Protecting Digital Signal Processing Cores Used in CE Devices [Hardware Matters]. IEEE Consumer Electron. Mag. 8(1): 92-94 (2019) - 2018
- [j4]Dipanjan Roy, Pallabi Sarkar, Anirban Sengupta, Mrinal Kanti Naskar:
Optimizing DSP Cores Using Design Transformation [Hardware Matters]. IEEE Consumer Electron. Mag. 7(4): 91-94 (2018) - [c8]Anirban Sengupta, Shubha Neema, Pallabi Sarkar, Sri Harsha P, Saraju P. Mohanty, Mrinal Kanti Naskar:
Obfuscation of Fault Secured DSP Design Through Hybrid Transformation. ISVLSI 2018: 732-737 - 2017
- [j3]Pallabi Sarkar, Anirban Sengupta, Santosh Rathlavat, Mrinal Kanti Naskar:
Designing Low-Cost Hardware Accelerators for CE Devices [Hardware Matters]. IEEE Consumer Electron. Mag. 6(4): 140-149 (2017) - [c7]Pallabi Sarkar, Anirban Sengupta, Santosh Rathlavat, Mrinal Kanti Naskar:
A Firefly Algorithm Driven Approach for High Level Synthesis. iNIS 2017: 15-19 - 2015
- [c6]Pallabi Sarkar, Anirban Sengupta, Mrinal Kanti Naskar:
GA driven integrated exploration of loop unrolling factor and datapath for optimal scheduling of CDFGs during high level synthesis. CCECE 2015: 75-80 - 2013
- [c5]Tulasi Krishna, Priyam Sachdeva, Suraj Kumar Dhanuka, Mohit Gagrani, Pallabi Sarkar:
A multi parametric optimization based novel approach for an efficient design space exploration for ASIC design. ICACCI 2013: 868-873 - 2012
- [j2]Anirban Sengupta, Reza Sedaghat, Pallabi Sarkar:
Rapid exploration of integrated scheduling and module selection in high level synthesis for application specific processor design. Microprocess. Microsystems 36(4): 303-314 (2012) - [j1]Anirban Sengupta, Reza Sedaghat, Pallabi Sarkar:
A multi structure genetic algorithm for integrated design space exploration of scheduling and allocation in high level synthesis for DSP kernels. Swarm Evol. Comput. 7: 35-46 (2012) - 2011
- [c4]Anirban Sengupta, Reza Sedaghat, Pallabi Sarkar:
Integrated design space exploration based on power-performance trade-off using genetic algorithm. ACAI 2011: 77-81 - [c3]Pallabi Sarkar, Reza Sedaghat, Anirban Sengupta:
Application specific processor vs. microblaze soft core RISC processor: FPGA based performance and CPR analysis. ACAI 2011: 82-85 - [c2]Anirban Sengupta, Reza Sedaghat, Pallabi Sarkar, Summit Sehgal:
Integrated scheduling, allocation and binding in High Level Synthesis for performance-area tradeoff of digital media applications. CCECE 2011: 533-537 - [c1]Anirban Sengupta, Reza Sedaghat, Pallabi Sarkar, Summit Sehgal:
Priority function based power efficient rapid Design Space Exploration of scheduling and module selection in high level synthesis. CCECE 2011: 538-543
Coauthor Index
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