default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID20th PATMOS 2010: Grenoble, France
- René van Leuken, Gilles Sicard:
Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation - 20th International Workshop, PATMOS 2010, Grenoble, France, September 7-10, 2010, Revised Selected Papers. Lecture Notes in Computer Science 6448, Springer 2011, ISBN 978-3-642-17751-4
Design Flows
- Tanguy Sassolas, Nicolas Ventroux, Nassima Boudouani, Guillaume Blanc:
A Power-Aware Online Scheduling Algorithm for Streaming Applications in Embedded MPSoC. 1-10 - Christian Bachmann, Andreas Genser, Christian Steger, Reinhold Weiß, Josef Haid:
An Automated Framework for Power-Critical Code Region Detection and Power Peak Optimization of Embedded Software. 11-20 - Martin Gag, Tim Wegner, Dirk Timmermann
:
System Level Power Estimation of System-on-Chip Interconnects in Consideration of Transition Activity and Crosstalk. 21-30 - Ioannis Kouretas, Vassilis Paliouras:
Residue Arithmetic for Designing Low-Power Multiply-Add Units. 31-40
Circuit Techniques 1
- Abhishek Jain, Andrea Veggetti, Dennis Crippa, Pierluigi Rolandi:
An On-Chip Flip-Flop Characterization Circuit. 41-50 - Lida Ramezani:
A Low-Voltage Log-Domain Integrator Using MOSFET in Weak Inversion. 51-61 - Massimo Alioto, Elio Consoli, Gaetano Palumbo:
Physical Design Aware Comparison of Flip-Flops for High-Speed Energy-Efficient VLSI Circuits. 62-72 - Dimitris Bekiaris, Antonis Papanikolaou, Christos Papameletis, Dimitrios Soudris, George Economakos, Kiamal Z. Pekmestzi:
A Temperature-Aware Time-Dependent Dielectric Breakdown Analysis Framework. 73-83
Low Power Circuits
- Cristiano Lazzari, Jorge R. Fernandes, Paulo F. Flores, José Monteiro:
An Efficient Low Power Multiple-Value Look-Up Table Targeting Quaternary FPGAs. 84-93 - Pascal Vivet, Edith Beigné, Hugo Lebreton, Nacer-Eddine Zergainoh:
On Line Power Optimization of Data Flow Multi-core Architecture Based on Vdd-Hopping for Local DVFS. 94-104 - Abdullah Baz, Delong Shang, Fei Xia, Alexandre Yakovlev:
Self-Timed SRAM for Energy Harvesting Systems. 105-115 - Pablo Carazo, Rubén Apolloni, Fernando Castro, Daniel Chaver, Luis Piñuel, Francisco Tirado:
L1 Data Cache Power Reduction Using a Forwarding Predictor. 116-125
Self-Timed Circuits
- Mohsen Raji, Alireza Tajary, Behnam Ghavami, Hossein Pedram, Hamid R. Zarandi:
Statistical Leakage Power Optimization of Asynchronous Circuits Considering Process Variations. 126-136 - Oussama Elissati, Eslam Yahya, Sébastien Rieubon, Laurent Fesquet:
Optimizing and Comparing CMOS Implementations of the C-Element in 65nm Technology: Self-Timed Ring Case. 137-149 - Julian J. H. Pontes, Matheus T. Moreira, Fernando Moraes, Ney Calazans:
Hermes-A - An Asynchronous NoC Router with Distributed Routing. 150-159 - Alberto García Ortiz, Leandro Soares Indrusiak:
Practical and Theoretical Considerations on Low-Power Probability-Codes for Networks-on-Chip. 160-169
Process Variation
- Bahman Kheradmand Boroujeni, Christian Piguet, Yusuf Leblebici:
Logic Architecture and VDD Selection for Reducing the Impact of Intra-die Random VT Variations on Timing. 170-179 - Marco Lanuzza, Raffaele De Rose, Fabio Frustaci, Stefania Perri, Pasquale Corsonello:
Impact of Process Variations on Pulsed Flip-Flops: Yield Improving Circuit-Level Techniques and Comparative Analysis. 180-189 - Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs:
Transistor-Level Gate Modeling for Nano CMOS Circuit Verification Considering Statistical Process Variations. 190-199 - Christoph Knoth, Irina Eichwald, Petra Nordholz, Ulf Schlichtmann:
White-Box Current Source Modeling Including Parameter Variation and Its Application in Timing Simulation. 200-210
Circuit Techniques 2
- Abdelkrim Kamel Oudjida, Ahmed Liacha, Mohamed Lamine Berrandjia, Rachid Tiar:
Controlled-Precision Pure-Digital Square-Wave Frequency Synthesizer. 211-217 - Oliver Schrape, Frank Winkler, Steffen Zeidler, Markus Petri, Eckhard Grass, Ulrich Jagdhold:
An All-Digital Phase-Locked Loop with High Resolution for Local On-Chip Clock Synthesis. 218-227 - Jingwei Lu, Wing-Kai Chow, Chiu-Wing Sham:
Clock Network Synthesis with Concurrent Gate Insertion. 228-237 - Victor Lomné, Philippe Maurine, Lionel Torres, Thomas Ordas, Mathieu Lisart, Jérome Toublanc:
Modeling Time Domain Magnetic Emissions of ICs. 238-249
Special Session 1: High-Level Modeling of Power-Aware Heterogeneous Designs in SystemC-AMS (Abstracts)
- Jan Haase, Christoph Grimm:
Power Profiling of Embedded Analog/Mixed-Signal Systems. 250 - Daniel Chillet:
Open-People: Open Power and Energy Optimization PLatform and Estimator. 251 - François Pêcheux, Khouloud Zine el Abidine, Alain Greiner:
Early Power Estimation in Heterogeneous Designs Using SoCLib and SystemC-AMS. 252
Special Session 2: Minalogic (Abstracts)
- Marc Renaudin:
ASTEC: Asynchronous Technology for Low Power and Secured Embedded Systems. 253 - Laurent Maillet-Contoz:
OPENTLM and SOCKET: Creating an Open EcoSystem for Virtual Prototyping of Complex SOCs. 254
Keynotes (Abstracts)
- Kiyoo Itoh:
Variability-Conscious Circuit Designs for Low-Voltage Memory-Rich Nano-Scale CMOS LSIs. 255 - Marc Belleville:
3D Integration for Digital and Imagers Circuits: Opportunities and Challenges. 256 - Sébastien Marchal:
Signing Off Industrial Designs on Evolving Technologies. 257
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-11-07 20:40 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
