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Steffen Zeidler 0001
Person information
- affiliation (PhD 2013): Brandenburg University of Technology, Germany
Other persons with the same name
- Steffen Zeidler 0002 — Technische Hochschule Karl-Marx-Stadt, Germany
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2020 – today
- 2021
- [j3]Oliver Schrape, Marko S. Andjelkovic, Anselm Breitenreiter, Steffen Zeidler, Alexey Balashov, Milos Krstic:
Design and Evaluation of Radiation-Hardened Standard Cell Flip-Flops. IEEE Trans. Circuits Syst. I Regul. Pap. 68(11): 4796-4809 (2021) - [c15]Oliver Schrape, Anselm Breitenreiter, Carsten Schulze, Steffen Zeidler, Milos Krstic:
Radiation-Hardness-by-Design Latch-based Triple Modular Redundancy Flip-Flops. LASCAS 2021: 1-4 - 2020
- [c14]Steffen Zeidler, Oliver Schrape, Anselm Breitenreiter, Milos Krstic:
A Glitch-free Clock Multiplexer for Non-Continuously Running Clocks. DSD 2020: 11-15
2010 – 2019
- 2019
- [c13]Oliver Schrape, Anselm Breitenreiter, Steffen Zeidler, Milos Krstic:
Aspects on Timing Modeling of Radiation-Hardness by Design Standard Cell-Based △TMR Flip-Flops. DSD 2019: 639-642 - [c12]Anselm Breitenreiter, Stefan Weidling, Oliver Schrape, Steffen Zeidler, Pedro Reviriego, Milos Krstic:
Selective Fault Tolerance by Counting Gates with Controlling Value. IOLTS 2019: 15-20 - 2016
- [j2]Steffen Zeidler, Xin Fan, Oliver Schrape, Milos Krstic:
An Early Stage Design Flow for Switching Noise Attenuation. J. Circuits Syst. Comput. 25(3): 1640022:1-1640022:21 (2016) - [j1]Xin Fan, Mikkel B. Stegmann, Oliver Schrape, Steffen Zeidler, Isac G. Jensen, Jannich Thorsen, Tobias Bjerregaard, Milos Krstic:
Frequency-Domain Optimization of Digital Switching Noise Based on Clock Scheduling. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(7): 982-993 (2016) - [c11]Milan Babic, Steffen Zeidler, Milos Krstic:
GALS Partitioning Methodology for Substrate Noise Reduction in Mixed-Signal Integrated Circuits. ASYNC 2016: 67-74 - 2015
- [c10]Steffen Zeidler, Xin Fan, Oliver Schrape, Milos Krstic:
A Design Preconditioning Flow for Low-Noise Circuits. DDECS 2015: 191-196 - [c9]Steffen Zeidler, Milos Krstic:
A survey about testing asynchronous circuits. ECCTD 2015: 1-4 - 2013
- [b1]Steffen Zeidler:
Enabling functional tests of asynchronous circuits using a test processor solution. Brandenburg University of Technology, 2013, pp. 1-214 - [c8]Steffen Zeidler, Michael Goderbauer, Milos Krstic:
Design of a low-power asynchronous elliptic curve cryptography coprocessor. ICECS 2013: 569-572 - 2012
- [c7]Steffen Zeidler, Christoph Wolf, Milos Krstic, Rolf Kraemer:
Functional Pattern Generation for Asynchronous Designs in a Test Processor Environment. Asian Test Symposium 2012: 296-301 - [c6]Eckhard Grass, Milos Krstic, Xin Fan, Steffen Zeidler:
Asynchronous circuit design: From basics to practical applications. DDECS 2012: 5 - 2011
- [c5]Steffen Zeidler, Christoph Wolf, Milos Krstic, Frank Vater, Rolf Kraemer:
Design of a Test Processor for Asynchronous Chip Test. Asian Test Symposium 2011: 244-250 - [c4]Christoph Wolf, Steffen Zeidler, Milos Krstic, Rolf Kraemer:
Overview on ATE Test and Debugging Methods for Asynchronous Circuits. MTV 2011: 16-21 - 2010
- [c3]Steffen Zeidler, Alexandre V. Bystrov, Milos Krstic, Rolf Kraemer:
On-line testing of bundled-data asynchronous handshake protocols. IOLTS 2010: 261-267 - [c2]Oliver Schrape, Frank Winkler, Steffen Zeidler, Markus Petri, Eckhard Grass, Ulrich Jagdhold:
An All-Digital Phase-Locked Loop with High Resolution for Local On-Chip Clock Synthesis. PATMOS 2010: 218-227
2000 – 2009
- 2009
- [c1]Steffen Zeidler, Marcus Ehrig, Milos Krstic, Michael Augustin, Christoph Wolf, Rolf Kraemer:
Ultra low cost asynchronous handshake checker. IOLTS 2009: 262-268
Coauthor Index
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