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ORCIDJulian J. H. Pontes
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2020 – today
- 2021
[j1]Pascal Vivet
, Eric Guthmuller, Yvain Thonnart, Gaël Pillonnet, César Fuguet Tortolero, Ivan Miro-Panades, Guillaume Moritz, Jean Durupt, Christian Bernard, Didier Varreau, Julian J. H. Pontes, Sébastien Thuries, David Coriat, Michel Harrand, Denis Dutoit, Didier Lattard, Lucile Arnaud, Jean Charbonnier, Perceval Coudrain, Arnaud Garnier, Frédéric Berger, Alain Gueugnot, Alain Greiner, Quentin L. Meunier, Alexis Farcy, Alexandre Arriordaz, Séverine Cheramy, Fabien Clermidy:
IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management. IEEE J. Solid State Circuits 56(1): 79-97 (2021)- 2020
- [c13]Pascal Vivet, Eric Guthmuller, Yvain Thonnart, Gaël Pillonnet, Guillaume Moritz, Ivan Miro-Panades, César Fuguet Tortolero, Jean Durupt, Christian Bernard, Didier Varreau, Julian J. H. Pontes, Sébastien Thuries, David Coriat, Michel Harrand, Denis Dutoit, Didier Lattard, Lucile Arnaud, Jean Charbonnier, Perceval Coudrain, Arnaud Garnier, Frédéric Berger, Alain Gueugnot, Alain Greiner, Quentin L. Meunier, Alexis Farcy, Alexandre Arriordaz, Séverine Cheramy, Fabien Clermidy:
2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm2 Inter-Chiplet Interconnects and 156mW/mm2@ 82%-Peak-Efficiency DC-DC Converters. ISSCC 2020: 46-48
2010 – 2019
- 2015
- [c12]Julian J. H. Pontes, Pascal Vivet, Yvain Thonnart:
Two-phase protocol converters for 3D asynchronous 1-of-n data links. ASP-DAC 2015: 154-159 - 2014
- [c11]Matheus T. Moreira, Julian J. H. Pontes, Ney Laert Vilar Calazans:
Tradeoffs between RTO and RTZ in WCHB QDI asynchronous design. ISQED 2014: 692-699 - 2013
- [c10]Julian J. H. Pontes, Ney Calazans, Pascal Vivet:
Parity check for m-of-n delay insensitive codes. IOLTS 2013: 157-162 - [c9]Julian J. H. Pontes, Ney Calazans, Pascal Vivet:
H2A: A hardened asynchronous network on chip. SBCCI 2013: 1-6 - 2012
- [b1]Julian J. H. Pontes:
Soft error mitigation in asynchronous networks on chip. Pontifícia Universidade Católica do Rio Grande do Sul, Porto Alegre, Brazil, 2012 - [c8]Julian J. H. Pontes, Ney Calazans, Pascal Vivet:
Adding Temporal Redundancy to Delay Insensitive Codes to Mitigate Single Event Effects. ASYNC 2012: 142-149 - [c7]Julian J. H. Pontes, Ney Calazans, Pascal Vivet:
An accurate Single Event Effect digital design flow for reliable system level design. DATE 2012: 224-229 - 2011
- [c6]Matheus T. Moreira, Bruno Cruz de Oliveira, Julian J. H. Pontes, Fernando Moraes, Ney Calazans:
Adapting a C-element design flow for low power. ICECS 2011: 45-48 - [c5]Matheus T. Moreira, Bruno Cruz de Oliveira, Julian J. H. Pontes, Ney Calazans:
A 65nm standard cell set and flow dedicated to automated asynchronous circuits design. SoCC 2011: 99-104 - 2010
- [c4]Julian J. H. Pontes, Matheus T. Moreira, Fernando Moraes, Ney Calazans:
Hermes-A - An Asynchronous NoC Router with Distributed Routing. PATMOS 2010: 150-159 - [c3]Julian J. H. Pontes, Matheus T. Moreira, Fernando Moraes, Ney Calazans:
Hermes-AA: A 65nm asynchronous NoC router with adaptive routing. SoCC 2010: 493-498
2000 – 2009
- 2008
- [c2]Julian J. H. Pontes, Matheus T. Moreira, Rafael Soares, Ney Laert Vilar Calazans:
Hermes-GLP: A GALS Network on Chip Router with Power Control Techniques. ISVLSI 2008: 347-352 - 2007
- [c1]Julian J. H. Pontes, Rafael Soares, Ewerson Carvalho, Fernando Moraes, Ney Calazans:
SCAFFI: An intrachip FPGA asynchronous interface based on hard macros. ICCD 2007: 541-546
Coauthor Index
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