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ORCIDEric Guthmuller
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2020 – today
- 2024
[j2]Eric Guthmuller
, César Fuguet, Andrea Bocco, Jérôme Fereyre, Riccardo Alidori, Ihsane Tahir, Yves Durand:
Xvpfloat: RISC-V ISA Extension for Variable Extended Precision Floating Point Computation. IEEE Trans. Computers 73(7): 1683-1697 (2024)- [c14]Mathieu Toubeix, Eric Guthmuller, Adrian Evans, Tristan Meunier:
A Scalable Low-Latency FPGA Architecture for Spin Qubit Control Through Direct Digital Synthesis. DATE 2024: 1-2 - 2022
- [c13]Yves Durand, Eric Guthmuller, César Fuguet Tortolero, Jérôme Fereyre, Andrea Bocco, Riccardo Alidori:
Accelerating Variants of the Conjugate Gradient with the Variable Precision Processor. ARITH 2022: 51-57 - 2021
- [j1]Pascal Vivet, Eric Guthmuller, Yvain Thonnart, Gaël Pillonnet, César Fuguet Tortolero, Ivan Miro-Panades, Guillaume Moritz, Jean Durupt, Christian Bernard, Didier Varreau, Julian J. H. Pontes, Sébastien Thuries, David Coriat, Michel Harrand, Denis Dutoit, Didier Lattard, Lucile Arnaud, Jean Charbonnier, Perceval Coudrain, Arnaud Garnier, Frédéric Berger, Alain Gueugnot, Alain Greiner, Quentin L. Meunier, Alexis Farcy, Alexandre Arriordaz, Séverine Cheramy, Fabien Clermidy:
IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management. IEEE J. Solid State Circuits 56(1): 79-97 (2021) - [c12]Valentin Egloff, Jean-Philippe Noel, Maha Kooli, Bastien Giraud, Lorenzo Ciampolini, Roman Gauchi, César Fuguet Tortolero, Eric Guthmuller, Mathieu Moreau, Jean-Michel Portal:
Storage Class Memory with Computing Row Buffer: A Design Space Exploration. DATE 2021: 1-6 - 2020
- [c11]Pascal Vivet, Eric Guthmuller, Yvain Thonnart, Gaël Pillonnet, Guillaume Moritz, Ivan Miro-Panades, César Fuguet Tortolero, Jean Durupt, Christian Bernard, Didier Varreau, Julian J. H. Pontes, Sébastien Thuries, David Coriat, Michel Harrand, Denis Dutoit, Didier Lattard, Lucile Arnaud, Jean Charbonnier, Perceval Coudrain, Arnaud Garnier, Frédéric Berger, Alain Gueugnot, Alain Greiner, Quentin L. Meunier, Alexis Farcy, Alexandre Arriordaz, Séverine Cheramy, Fabien Clermidy:
2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm2 Inter-Chiplet Interconnects and 156mW/mm2@ 82%-Peak-Efficiency DC-DC Converters. ISSCC 2020: 46-48
2010 – 2019
- 2018
- [c10]Julie Dumas, Eric Guthmuller, Frédéric Pétrot:
Dynamic Coherent Cluster: A Scalable Sharing Set Management Approach. ASAP 2018: 1-8 - [c9]Eric Guthmuller, César Fuguet Tortolero, Pascal Vivet, Christian Bernard, Ivan Miro Panades, Jean Durupt, E. Beignc, Didier Lattard, Séverine Cheramy, Alain Greiner, Quentin L. Meunier, Pirouz Bazargan-Sabet:
A 29 Gops/Watt 3D-Ready 16-Core Computing Fabric with Scalable Cache Coherent Architecture Using Distributed L2 and Adaptive L3 Caches. ESSCIRC 2018: 318-321 - 2017
- [c8]Julie Dumas, Eric Guthmuller, César Fuguet Tortolero, Frédéric Pétrot:
A Method for Fast Evaluation of Sharing Set Management Strategies in Cache Coherence Protocols. ARCS 2017: 111-123 - [c7]Julie Dumas, Eric Guthmuller, César Fuguet Tortolero, Frédéric Pétrot:
Trace-driven exploration of sharing set management strategies for cache coherence in manycores. NEWCAS 2017: 77-80 - 2015
- [c6]Pascal Vivet, Christian Bernard, Fabien Clermidy, Denis Dutoit, Eric Guthmuller, Ivan Miro Panades, Gaël Pillonnet, Yvain Thonnart, Arnaud Garnier, Didier Lattard, Amandine Jouve, Franck Bana, Thierry Mourier, Séverine Cheramy:
3D advanced integration technology for heterogeneous systems. 3DIC 2015: FS6.1-FS6.3 - [c5]Pascal Vivet, Christian Bernard, Eric Guthmuller, Ivan Miro Panades, Yvain Thonnart, Fabien Clermidy:
Interconnect Challenges for 3D Multi-cores: From 3D Network-on-Chip to Cache Interconnects. ISVLSI 2015: 615-620 - 2013
- [c4]Denis Dutoit, Eric Guthmuller, Ivan Miro Panades:
3D integration for power-efficient computing. DATE 2013: 779-784 - [c3]Fabien Clermidy, Denis Dutoit, Eric Guthmuller, Ivan Miro Panades, Pascal Vivet:
3D stacking for multi-core architectures: From WIDEIO to distributed caches. ISCAS 2013: 537-540 - [c2]Eric Guthmuller, Ivan Miro Panades, Alain Greiner:
Architectural exploration of a fine-grained 3D cache for high performance in a manycore context. VLSI-SoC 2013: 302-307 - 2012
- [c1]Eric Guthmuller, Ivan Miro Panades, Alain Greiner:
Adaptive Stackable 3D Cache Architecture for Manycores. ISVLSI 2012: 39-44
Coauthor Index
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