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ORCID31st ASAP 2020: Manchester, UK
- 31st IEEE International Conference on Application-specific Systems, Architectures and Processors , ASAP 2020, Manchester, United Kingdom, July 6-8, 2020. IEEE 2020, ISBN 978-1-7281-7147-0
- Ryohei Kobayashi
, Norihisa Fujita, Yoshiki Yamaguchi, Taisuke Boku, Kohji Yoshikawa, Makito Abe, Masayuki Umemura:
Accelerating Radiative Transfer Simulation with GPU-FPGA Cooperative Computation. 9-16 - Qian Xu, Guowei Sun, Gang Qu:
BWOLF: Bit-Width Optimization for Statistical Divergence with -Logarithmic Functions. 165-172 - Nuno Neves, Pedro Tomás, Nuno Roma:
Reconfigurable Stream-based Tensor Unit with Variable-Precision Posit Arithmetic. 149-156 - Shuhei Yoshida, Yuta Ukon, Shoko Ohteru, Hiroyuki Uzawa, Namiko Ikeda, Koyo Nitta:
FPGA-Based Network Microburst Analysis System with Flow Specification and Efficient Packet Capturing. 29-32 - Mikhail Asiatici, Damian Maiorano, Paolo Ienne:
FPGAs in the Datacenters: the Case of Parallel Hybrid Super Scalar String Sample Sort. 133-140 - Moritz Bärthel, Jochen Rust, Steffen Paul:
Combining Fixed-Point and SORN Arithmetic in a MIMO BPSK-Symbol Detection Architecture. 181-184 - Hsin-Yu Ting, Tootiya Giyahchi, Ardalan Amiri Sani, Eli Bozorgzadeh:
Dynamic Sharing in Multi-accelerators of Neural Networks on an FPGA Edge Device. 197-204 - Leonardo Alves Dias, Maria G. F. Coutinho, Elena I. Gaura, Marcelo A. C. Fernandes:
A New Hardware Approach to Self-Organizing Maps. 205-212 - Jiuxi Meng, Ce Guo, Nadeen Gebara, Wayne Luk:
Fast and Accurate Training of Ensemble Models with FPGA-based Switch. 81-84 - Cristian Sestito, Fanny Spagnolo, Pasquale Corsonello, Stefania Perri:
An Efficient Convolution Engine based on the À-trous Spatial Pyramid Pooling. 77-80 - Joel Mandebi Mbongue, Alex Shuping, Pankaj Bhowmik, Christophe Bobda:
Architecture Support for FPGA Multi-tenancy in the Cloud. 125-132 - Jan Richter-Brockmann, Tim Güneysu:
Improved Side-Channel Resistance by Dynamic Fault-Injection Countermeasures. 117-124 - Matthew Naylor, Simon W. Moore, Andrey Mokhov, David B. Thomas, Jonathan R. Beaumont, Shane T. Fleming, A. Theodore Markettos, Thomas Bytheway, Andrew D. Brown:
Termination detection for fine-grained message-passing architectures. 17-24 - Dirk Koch, Frank Hannig, Javier Navaridas:
Message from the Conference Chairs - ASAP 2020. i-ii - Somdip Dey, Amit Kumar Singh, Dilip Kumar Prasad, Klaus D. McDonald-Maier:
Temporal Motionless Analysis of Video using CNN in MPSoC. 73-76 - Mohammad Pivezhandi, Phillip H. Jones, Joseph Zambreno:
ParaHist: FPGA Implementation of Parallel Event-Based Histogram for Optical Flow Calculation. 185-188 - Seongyoung Kang, Jinyeong Moon, Sang-Woo Jun:
FPGA-Accelerated Time Series Mining on Low-Power IoT Devices. 33-36 - Marcel Brand, Michael Witterauf, Alberto Bosio, Jürgen Teich:
Anytime Floating-Point Addition and Multiplication-Concepts and Implementations. 157-164 - Artur Podobas, Kentaro Sano, Satoshi Matsuoka:
A Template-based Framework for Exploring Coarse-Grained Reconfigurable Architectures. 1-8 - Aman Arora, Zhigang Wei, Lizy K. John:
Hamamu: Specializing FPGAs for ML Applications by Adding Hard Matrix Multiplier Blocks. 53-60 - Bingyi Zhang, Hanqing Zeng, Viktor K. Prasanna:
Hardware Acceleration of Large Scale GCN Inference. 61-68 - Zhigang Wei, Aman Arora, Pragenesh Patel, Lizy Kurian John:
Design Space Exploration for Softmax Implementations. 45-52 - Krishna Teja Chitty-Venkata, Arun K. Somani:
Array Aware Training/Pruning: Methods for Efficient Forward Propagation on Array-based Neural Network Accelerators. 37-44 - Riadh Ben Abdelhamid, Yoshiki Yamaguchi, Taisuke Boku:
Condensing an overload of parallel computing ingredients into a single architecture recipe. 25-28 - Mark G. Arnold, Ed Chester, Corey Johnson:
Training Neural Nets using only an Approximate Tableless LNS ALU. 69-72 - Armin Mehrabian, Volker J. Sorger, Tarek A. El-Ghazawi:
A Design Methodology for Post-Moore's Law Accelerators: The Case of a Photonic Neuromorphic Processor. 113-116 - Jessica Vandebon, José Gabriel F. Coutinho, Wayne Luk, Eriko Nurvitadhi, Mishali Naik:
SLATE: Managing Heterogeneous Cloud Functions. 141-148 - Mioara Joldes, Bogdan Pasca:
Efficient Floating-Point Implementation of the Probit Function on FPGAs. 173-180 - John Reuben, Stefan Pechmann:
A Parallel-friendly Majority Gate to Accelerate In-memory Computation. 93-100 - Dawen Xu, Ziyang Zhu, Cheng Liu, Ying Wang, Huawei Li, Lei Zhang, Kwang-Ting Cheng:
Persistent Fault Analysis of Neural Networks on FPGA-based Acceleration System. 85-92 - Taha Soliman, Ricardo Olivo, Tobias Kirchner, Cecilia De la Parra, Maximilian Lederer, Thomas Kämpfe, Andre Guntoro, Norbert Wehn:
Efficient FeFET Crossbar Accelerator for Binary Neural Networks. 109-112 - Nathaniel Joseph Tye, James Timothy Meech, Bilgesu Arif Bilgin, Phillip Stanley-Marbell:
A System for Generating Non-Uniform Random Variates using Graphene Field-Effect Transistors. 101-108 - Perry Gibson, José Cano, Jack Turner, Elliot J. Crowley, Michael F. P. O'Boyle, Amos J. Storkey:
Optimizing Grouped Convolutions on Edge Devices. 189-196 - Johnson Loh, Jianan Wen, Tobias Gemmeke:
Low-Cost DNN Hardware Accelerator for Wearable, High-Quality Cardiac Arrythmia Detection. 213-216
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