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2010 – 2019
- 2018
[c10]Panayiotis Alefragis
, George Theodoridis, Merkourios Katsimpris, Christos Valouxis, Christos Gogos, George Goulas, Nikolaos S. Voros, Simon Reder, Koray Kasnakli, Marcus Bednara, David Müller, Umut Durak, Jürgen Becker:
Mapping and Scheduling Hard Real Time Applications on Multicore Systems - The ARGO Approach. ARC 2018: 700-711- 2017
- [c9]Steven Derrien, Isabelle Puaut, Panayiotis Alefragis, Marcus Bednara, Harald Bucher, Clément David, Yann Debray, Umut Durak, Imen Fassi, Christian Ferdinand, Damien Hardy, Angeliki Kritikakou, Gerard K. Rauwerda, Simon Reder, Martin Sicks, Timo Stripf, Kim Sunesen, Timon D. ter Braak, Nikolaos S. Voros, Jürgen Becker:
WCET-aware parallelization of model-based applications for multi-cores: The ARGO approach. DATE 2017: 286-289
2000 – 2009
- 2004
- [c8]Ali Ahmadinia, Christophe Bobda, Marcus Bednara, Jürgen Teich:
A New Approach for On-line Placement on Reconfigurable Devices. IPDPS 2004 - [c7]Ali Ahmadinia, Christophe Bobda, Marcus Bednara, Jürgen Teich:
Real-Time Configuration Code Decompression for Dynamic FPGA Self-Reconfiguration. IPDPS 2004 - 2003
- [j2]Marcus Bednara, Klaus Danne, Markus Deppe, Oliver Oberschelp, Frank Slomka, Jürgen Teich:
Design and Implementation of Digital Linear Control Systems on Reconfigurable Hardware. EURASIP J. Adv. Signal Process. 2003(6): 594-602 (2003) - [j1]Marcus Bednara, Jürgen Teich:
Automatic Synthesis of FPGA Processor Arrays from Loop Algorithms. J. Supercomput. 26(2): 149-165 (2003) - [c6]Cornelia Grabbe, Marcus Bednara, Joachim von zur Gathen, Jamshid Shokrollahi, Jürgen Teich:
A High Performance VLIW Processor for Finite Field Arithmetic. IPDPS 2003: 189 - [c5]Cornelia Grabbe, Marcus Bednara, Jürgen Teich, Joachim von zur Gathen, Jamshid Shokrollahi:
FPGA designs of parallel high performance GF(2233) multipliers. ISCAS (2) 2003: 268-271 - 2002
- [c4]Marcus Bednara, M. Daldrup, Joachim von zur Gathen, Jamshid Shokrollahi, Jürgen Teich:
Reconfigurable Implementation of Elliptic Curve Crypto Algorithms. IPDPS 2002 - [c3]Marcus Bednara, M. Daldrup, Jürgen Teich, Joachim von zur Gathen, Jamshid Shokrollahi:
Tradeoff analysis of FPGA based elliptic curve cryptography. ISCAS (5) 2002: 797-800 - [c2]Marcus Bednara, Frank Hannig, Jürgen Teich:
Generation of Distributed Loop Control. Embedded Processor Design Challenges 2002: 154-170 - 2000
- [c1]Marcus Bednara, Oliver Beyer, Jürgen Teich, Rolf Wanka:
Tradeoff Analysis and Architecture Design of a Hybrid Hardware/Software Sorter. ASAP 2000: 299-308
Coauthor Index
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