default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDMEMSYS 2024: Washington, DC, USA
- Proceedings of the International Symposium on Memory Systems, MEMSYS 2024, Washington, DC, USA, 30 September 2024 - 3 October 2024. ACM 2024, ISBN 979-8-4007-1091-9
- Johnathan Alsop
, Shaizeen Aga, Mohamed Assem Ibrahim, Mahzabeen Islam, Nuwan Jayasena, Andrew McCrabb:
PIM-Potential: Broadening the Acceleration Reach of PIM Architectures. 1-12 - Mohamed Assem Ibrahim, Shaizeen Aga:
Pimacolaba: Collaborative Acceleration for FFT on Commercial Processing-In-Memory Architectures. 13-25 - Derek Christ, Lukas Steiner, Matthias Jung, Norbert Wehn:
PIMSys: A Virtual Prototype for Processing in Memory. 26-33 - Robert Trout, David Lynch:
Sadram Arithmetic in C++. 34-37 - Lita Yang, Changjung Kao, Sriseshan Srikanth, Huseyin Ekin Sumbul, Tony F. Wu, Huichu Liu, Edith Beigné:
Characterization and Design of 3D-Stacked Memory for Image Signal Processing on AR/VR Devices. 38-44 - Berk Saglam, Nam Ho, Carlos Falquez, Antoni Portero, Fabian Schätzle, Estela Suarez, Dirk Pleiter:
Data Prefetching on Processors with Heterogeneous Memory. 45-60 - Andronicus Rajasukumar, Tianchi Zhang, Ruiqi Xu, Andrew A. Chien:
UpDown: A Novel Architecture for Unlimited Memory Parallelism. 61-77 - Samiksha Verma, Virendra Singh:
SMS: Solving Many-sided RowHammer. 78-88 - Prabuddha Sinha, Krishna Pratik BV, Shirshendu Das, Venkata Kalyan Tavva:
PROLONG: Priority based Write Bypassing Technique for Longer Lifetime in STT-RAM based LLC. 89-103 - Waqar Hassan Mir, Neeraj Goel, Venkata Kalyan Tavva:
CARDR: DRAM Cache Assisted Ransomware Detection and Recovery in SSDs. 104-115 - Rui Xie, Linsen Ma, Alex Zhong, Feng Chen, Tong Zhang:
ZipCache: A DRAM/SSD Cache with Built-in Transparent Compression. 116-128 - Shaotong Sun, Yifan Zhu, Xingzhi Ye, Chen Ding:
Measuring Data Access Latency in Large CPU Caches. 129-139 - Marcus Figorito, Vincent Michelini, Benjamin Reber, Alexander H. Kneipp, Matthew Gould, Chen Ding, Linlin Chen, Dorin Patru:
Implementation of a Two-Level Programmable Cache Emulation and Test System. 140-156 - Chandrahas Tirumalasetty, Narasimha Reddy Annapareddy:
Contention aware DRAM caching for CXL-enabled pooled memory. 157-171 - Jianbo Wu, Jie Liu, Gokcen Kestor, Roberto Gioiosa, Dong Li, Andres Marquez:
Performance Study of CXL Memory Topology. 172-177 - Joshua Suetterlein, Joseph B. Manzano, Andres Marquez:
Synchronization for CXL Based Memory. 178-185 - Beatrice Branchini, Ian Di Dio Lavore, Vito Giovanni Castellana, Marco D. Santambrogio:
Programming the Future: the Essential Role of System Topology Awareness in Heterogeneous Disaggregated Environments. 186-191 - Anusha Devulapally, Mahantesh Halappanavar, Amit Puri, Vijaykrishnan Narayanan, Andres Marquez:
Using Isoefficiency as a Metric to Assess Disaggregated Memory Systems for High Performance Computing. 192-197 - Yan Kang, Sayan Ghosh, Mahmut T. Kandemir, Andrés Márquez:
Studying CPU and memory utilization of applications on Fujitsu A64FX and Nvidia Grace Superchip. 198-207 - Sina Karimi, Kurt Keville:
A comparison of modern memory management schemes in HPC. 208-209 - Claudio Barone, Rishika Kushwah, Ankur Limaye, Vito Giovanni Castellana, Giovanni Gozzi, Michele Fiorito, Fabrizio Ferrandi, Antonino Tumeo:
To Cache or not to Cache? Exploring the Design Space of Tunable, HLS-generated Accelerators. 210-218 - Kevin Sheridan, Jered Dominguez-Trujillo, Galen M. Shipman, Patrick Lavin, Christopher Scott, Agustin Vaca Valverde, Richard W. Vuduc, Jeffrey Young:
A Workflow for the Synthesis of Irregular Memory Access Microbenchmarks. 219-234 - Abdur Razzak, Atanu Barai, Nandakishore Santhi, Abdel-Hameed A. Badawy:
Static Reuse Profile Estimation for Array Applications. 235-244 - Salvatore Servodio, Xiaoming Li:
Memory Efficiency Oriented Fine-Grain Representation and Optimization of FFT. 245-256 - Nils Wilbert, Stefan Wildermann, Jürgen Teich:
Hybrid Cache Design Under Varying Power Supply Stability - A Comparative Study. 257-269 - Yasodha Suriyakumar, Nathan R. Tallent, Andres Marquez, Karen L. Karavanic, Ozgur O. Kilic:
MemFriend: Understanding Memory Performance with Spatial-Temporal Affinity. 270-284
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-01-18 01:12 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
