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ORCIDHuseyin Ekin Sumbul
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2020 – today
- 2024
[j3]Huseyin Ekin Sumbul
, Jae-sun Seo, Daniel H. Morris, Edith Beigné:
A Fully Digital and Row-Pipelined Compute-in-Memory Neural Network Accelerator With System-on-Chip-Level Benchmarking for Augmented/Virtual Reality Applications. IEEE Micro 44(2): 61-70 (2024)- [c20]Tony F. Wu, Huichu Liu, Huseyin Ekin Sumbul, Lita Yang, Dipti Baheti, Jeremy Coriell, William Koven, Anu Krishnan, Mohit Mittal, Matheus Trevisan Moreira, Max Waugaman, Laurent Ye, Edith Beigné:
11.2 A 3D integrated Prototype System-on-Chip for Augmented Reality Applications Using Face-to-Face Wafer Bonded 7nm Logic at <2μm Pitch with up to 40% Energy Reduction at Iso-Area Footprint. ISSCC 2024: 210-212 - [c19]Lita Yang, Changjung Kao, Sriseshan Srikanth, Huseyin Ekin Sumbul, Tony F. Wu, Huichu Liu, Edith Beigné:
Characterization and Design of 3D-Stacked Memory for Image Signal Processing on AR/VR Devices. MEMSYS 2024: 38-44 - 2023
- [c18]Matheus Trevisan Moreira, William Koven, Tony F. Wu, Huseyin Ekin Sumbul, Edith Beigné:
A QDI Interconnect for 3D Systems Using Industry Standard EDA and Cell Libraries. ASYNC 2023: 58-59 - 2022
- [c17]Huseyin Ekin Sumbul, Tony F. Wu, Yuecheng Li, Syed Shakib Sarwar, William Koven, Eli Murphy-Trotzky, Xingxing Cai, Elnaz Ansari, Daniel H. Morris, Huichu Liu, Doyun Kim, Edith Beigné:
System-Level Design and Integration of a Prototype AR/VR Hardware Featuring a Custom Low-Power DNN Accelerator Chip in 7nm Technology for Codec Avatars. CICC 2022: 1-8 - [c16]Linyan Mei, Huichu Liu, Tony F. Wu, Huseyin Ekin Sumbul, Marian Verhelst, Edith Beigné:
A Uniform Latency Model for DNN Accelerators with Diverse Architectures and Dataflows. DATE 2022: 220-225 - [c15]Daniel H. Morris, Huichu Liu, Tony F. Wu, Huseyin Ekin Sumbul, Elnaz Ansari, Alexandre Barachant, Jonathan Reid, Edith Beigné:
Co-Optimization of SRAM Circuits with Sequential Access Patterns in a 7nm SoC Achieving 58% Memory Energy Reduction for AR Applications. VLSI Technology and Circuits 2022: 216-217 - [i2]Dominika Przewlocka-Rus, Syed Shakib Sarwar, Huseyin Ekin Sumbul, Yuecheng Li, Barbara De Salvo:
Power-of-Two Quantization for Low Bitwidth and Hardware Compliant Neural Networks. CoRR abs/2203.05025 (2022) - [i1]Zhongnan Qu, Syed Shakib Sarwar, Xin Dong, Yuecheng Li, Huseyin Ekin Sumbul, Barbara De Salvo:
DRESS: Dynamic REal-time Sparse Subnets. CoRR abs/2207.00670 (2022) - 2021
- [j2]Phil C. Knag, Gregory K. Chen, Huseyin Ekin Sumbul, Raghavan Kumar, Steven K. Hsu, Amit Agarwal, Monodeep Kar, Seongjong Kim, Mark A. Anders, Himanshu Kaul, Ram K. Krishnamurthy:
A 617-TOPS/W All-Digital Binary Neural Network Accelerator in 10-nm FinFET CMOS. IEEE J. Solid State Circuits 56(4): 1082-1092 (2021) - 2020
- [c14]Amit Agarwal, Steven Hsu, Simeon Realov, Mark A. Anders, Gregory K. Chen, Monodeep Kar, Raghavan Kumar, Huseyin Sumbul, Phil C. Knag, Himanshu Kaul, Sanu Mathew, Mahesh Kumashikar, Ram Krishnamurthy, Vivek De:
25.7 Time-Borrowing Fast Mux-D Scan Flip-Flop with On-Chip Timing/Power/VMIN Characterization Circuits in 10nm CMOS. ISSCC 2020: 392-394 - [c13]Mark A. Anders, Himanshu Kaul, Seongjong Kim, Gregory K. Chen, Raghavan Kumar, Huseyin Ekin Sumbul, Phil C. Knag, Monodeep Kar, Steven K. Hsu, Amit Agarwal, Vikram B. Suresh, Sanu K. Mathew, Ram K. Krishnamurthy, Vivek De:
25.9 Reconfigurable Transient Current-Mode Global Interconnect Circuits in 10nm CMOS for High-Performance Processors with Wide Voltage-Frequency Operating Range. ISSCC 2020: 396-398 - [c12]Steven Hsu, Amit Agarwal, Simeon Realov, Mark A. Anders, Gregory K. Chen, Monodeep Kar, Raghavan Kumar, Huseyin Sumbul, Phil C. Knag, Himanshu Kaul, Vikram B. Suresh, Sanu Mathew, Iqbal Rajwani, Satish Damaraju, Ram Krishnamurthy, Vivek De:
Low-Clock-Power Digital Standard Cell IPs for High-Performance Graphics/AI Processors in 10nm CMOS. VLSI Circuits 2020: 1-2 - [c11]Monodeep Kar, Amit Agarwal, Steven Hsu, David Moloney, Gregory K. Chen, Raghavan Kumar, Huseyin Sumbul, Phil C. Knag, Mark A. Anders, Himanshu Kaul, Jonathan Byrne, Luca Sarti, Ram Krishnamurthy, Vivek De:
A Ray-Casting Accelerator in 10nm CMOS for Efficient 3D Scene Reconstruction in Edge Robotics and Augmented Reality Applications. VLSI Circuits 2020: 1-2 - [c10]Phil C. Knag, Gregory K. Chen, Huseyin Ekin Sumbul, Raghavan Kumar, Mark A. Anders, Himanshu Kaul, Steven K. Hsu, Amit Agarwal, Monodeep Kar, Seongjong Kim, Ram K. Krishnamurthy:
A 617 TOPS/W All Digital Binary Neural Network Accelerator in 10nm FinFET CMOS. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [j1]Gregory K. Chen, Raghavan Kumar, Huseyin Ekin Sumbul, Phil C. Knag, Ram K. Krishnamurthy:
A 4096-Neuron 1M-Synapse 3.8-pJ/SOP Spiking Neural Network With On-Chip STDP Learning and Sparse Weights in 10-nm FinFET CMOS. IEEE J. Solid State Circuits 54(4): 992-1002 (2019) - [c9]Eriko Nurvitadhi, Dongup Kwon, Ali Jafari, Andrew Boutros, Jaewoong Sim, Phillip Tomson, Huseyin Sumbul, Gregory K. Chen, Phil C. Knag, Raghavan Kumar, Ram Krishnamurthy, Sergey Gribok, Bogdan Pasca, Martin Langhammer, Debbie Marr, Aravind Dasu:
Why Compete When You Can Work Together: FPGA-ASIC Integration for Persistent RNNs. FCCM 2019: 199-207 - [c8]Eriko Nurvitadhi, Dongup Kwon, Ali Jafari, Andrew Boutros, Jaewoong Sim, Phillip Tomson, Huseyin Sumbul, Gregory K. Chen, Phil C. Knag, Raghavan Kumar, Ram Krishnamurthy, Debbie Marr, Sergey Gribok, Bogdan Pasca, Martin Langhammer, Aravind Dasu:
Evaluating and Enhancing Intel® Stratix® 10 FPGAs for Persistent Real-Time AI. FPGA 2019: 119 - 2018
- [c7]Gregory K. Chen, Raghavan Kumar, Huseyin Ekin Sumbul, Phil C. Knag, Ram K. Krishnamurthy:
A 4096-Neuron 1M-Synapse 3.8PJ/SOP Spiking Neural Network with On-Chip STDP Learning and Sparse Weights in 10NM FinFET CMOS. VLSI Circuits 2018: 255-256 - 2015
- [b1]Huseyin Ekin Sumbul:
A Novel Design Methodology for Synthesizing Application-Specific Logic-in-Memory Blocks. Carnegie Mellon University, USA, 2015 - [c6]Huseyin Ekin Sumbul, Kaushik Vaidyanathan, Qiuling Zhu, Franz Franchetti, Larry T. Pileggi:
A synthesis methodology for application-specific logic-in-memory designs. DAC 2015: 196:1-196:6 - 2014
- [c5]Kaushik Vaidyanathan, Bishnu Prasad Das, Huseyin Ekin Sumbul, Renzhi Liu, Larry T. Pileggi:
Building trusted ICs using split fabrication. HOST 2014: 1-6 - [c4]Kaushik Vaidyanathan, Renzhi Liu, Huseyin Ekin Sumbul, Qiuling Zhu, Franz Franchetti, Larry T. Pileggi:
Efficient and secure intellectual property (IP) design with split fabrication. HOST 2014: 13-18 - 2013
- [c3]Qiuling Zhu, Berkin Akin, Huseyin Ekin Sumbul, Fazle Sadi, James C. Hoe, Larry T. Pileggi, Franz Franchetti:
A 3D-stacked logic-in-memory accelerator for application-specific data intensive computing. 3DIC 2013: 1-7 - [c2]Qiuling Zhu, Tobias Graf, Huseyin Ekin Sumbul, Larry T. Pileggi, Franz Franchetti:
Accelerating sparse matrix-matrix multiplication with 3D-stacked logic-in-memory hardware. HPEC 2013: 1-6 - 2010
- [c1]Zubair Nawaz, Koen Bertels, Huseyin Ekin Sumbul:
Fast Smith-Waterman hardware implementation. IPDPS Workshops 2010: 1-4
Coauthor Index
aka: Ram K. Krishnamurthy
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