default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDACM Transactions on Reconfigurable Technology and Systems, Volume 2
Volume 2, Number 1, March 2009
- Patrick Schaumont
, Alex K. Jones, Steve Trimberger:
Guest Editors' Introduction to Security in Reconfigurable Systems Design. 1:1-1:6 - Maurice Keller, Andrew Byrne, William P. Marnane:
Elliptic Curve Cryptography on FPGA for Low-Power Applications. 2:1-2:20 - Robert P. McEvoy, Colin C. Murphy, William P. Marnane, Michael Tunstall:
Isolated WDDL: A Hiding Countermeasure for Differential Power Analysis on FPGAs. 3:1-3:23 - Laurent Sauvage, Sylvain Guilley, Yves Mathieu:
Electromagnetic Radiations of FPGAs: High Spatial Resolution Cartography and Attack on a Cryptographic Module. 4:1-4:24 - Mehrdad Majzoobi, Farinaz Koushanfar, Miodrag Potkonjak:
Techniques for Design and Implementation of Secure Reconfigurable PUFs. 5:1-5:33 - Shantanu Dutt, Li Li:
Trust-Based Design and Check of FPGA Circuits Using Two-Level Randomized ECC Structures. 6:1-6:36
Volume 2, Number 2, June 2009
- Hideharu Amano, Tadao Nakamura:
Guest Editors' Introduction: ICFPT 2007. 7:1-7:2 - Weisheng Zhao, Eric Belhaire, Claude Chappert, Bernard Dieny, Guillaume Prenat:
TAS-MRAM-Based Low-Power High-Speed Runtime Reconfiguration (RTR) FPGA. 8:1-8:19 - Dirk Koch, Christian Beckhoff, Jürgen Teich:
Hardware Decompression Techniques for FPGA-Based Embedded Systems. 9:1-9:23 - Justin S. J. Wong, N. Pete Sedcole, Peter Y. K. Cheung:
Self-Measurement of Combinatorial Circuit Delays in FPGAs. 10:1-10:22 - G. Seetharaman, B. Venkataramani:
Automation Schemes for FPGA Implementation of Wave-Pipelined Circuits. 11:1-11:19 - Jason Yu, Christopher Eagleston, Christopher Han-Yu Chou, Maxime Perreault, Guy G. Lemieux:
Vector Processing as a Soft Processor Accelerator. 12:1-12:34 - Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay Kumar Verma, Seyed-Hosein Attarzadeh-Niaki, Chrysostomos Nicopoulos, Frank K. Gürkaynak, Philip Brisk, Yusuf Leblebici, Paolo Ienne:
Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs. 13:1-13:36 - Stephen Jang, Billy Chan, Kevin Chung, Alan Mishchenko:
WireMap: FPGA Technology Mapping for Improved Routability and Enhanced LUT Merging. 14:1-14:24 - Eric S. Chung, Michael Papamichael, Eriko Nurvitadhi, James C. Hoe, Ken Mai, Babak Falsafi:
ProtoFlex: Towards Scalable, Full-System Multiprocessor Simulations Using FPGAs. 15:1-15:32
Volume 2, Number 3, September 2009
- Michael Pellauer, Muralidaran Vijayaraghavan, Michael Adler, Arvind, Joel S. Emer:
A-Port Networks: Preserving the Timed Behavior of Synchronous Systems for Modeling on FPGAs. 16:1-16:26 - Jason Cong, Yi Zou:
FPGA-Based Hardware Acceleration of Lithographic Aerial Image Simulation. 17:1-17:29 - Taneem Ahmed, Paul D. Kundarewich, Jason Helge Anderson:
Packing Techniques for Virtex-5 FPGAs. 18:1-18:24 - Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne:
An FPGA Logic Cell and Carry Chain Configurable as a 6: 2 or 7: 2 Compressor. 19:1-19:42
Volume 2, Number 4, September 2009
- Katherine Compton, Roger F. Woods, Christos-Savvas Bouganis, Pedro C. Diniz:
Introduction to the Special Issue ARC'08. 20:1 - Qiwei Jin, David B. Thomas, Wayne Luk, Benjamin Cope:
Exploring Reconfigurable Architectures for Tree-Based Option Pricing Models. 21:1-21:17 - Maria E. Angelopoulou, Christos-Savvas Bouganis, Peter Y. K. Cheung, George A. Constantinides:
Robust Real-Time Super-Resolution on FPGA and an Application to Video Enhancement. 22:1-22:29 - Chia-Tien Dan Lo, Yi-Gang Tai:
Space Optimization on Counters for FPGA-Based Perl Compatible Regular Expressions. 23:1-23:18 - Nikolaos Vassiliadis, George Theodoridis, Spiridon Nikolaidis:
An Application Development Framework for ARISE Reconfigurable Processors. 24:1-24:30 - Ozana Silvia Dragomir, Todor P. Stefanov, Koen Bertels:
Optimal Loop Unrolling and Shifting for Reconfigurable Architectures. 25:1-25:24 - Keith D. Underwood, K. Scott Hemmert, Craig D. Ulmer:
From Silicon to Science: The Long Road to Production Reconfigurable Supercomputing. 26:1-26:15
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-11-22 19:46 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
