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ORCIDMaurice Keller
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2010 – 2019
- 2011
[j4]Tom English, Emanuel M. Popovici, Maurice Keller, William P. Marnane
:
Network-on-Chip interconnect for pairing-based cryptographic IP cores. J. Syst. Archit. 57(1): 95-108 (2011)
2000 – 2009
- 2009
- [j3]Maurice Keller, William P. Marnane:
Low Energy ASIC Elliptic Curve Processor. J. Low Power Electron. 5(1): 85-95 (2009) - [j2]Maurice Keller, Andrew Byrne, William P. Marnane:
Elliptic Curve Cryptography on FPGA for Low-Power Applications. ACM Trans. Reconfigurable Technol. Syst. 2(1): 2:1-2:20 (2009) - [c6]Tom English, Maurice Keller, Ka Lok Man, Emanuel M. Popovici, Michel P. Schellekens, William P. Marnane:
A low-power pairing-based cryptographic accelerator for embedded security applications. SoCC 2009: 369-372 - [p1]Maurice Keller, Robert Ronan, Andrew Byrne, Colin C. Murphy, William P. Marnane:
Hardware Implementation of Pairings. Identity-Based Cryptography 2009: 207-225 - 2008
- [c5]Maurice Keller, William P. Marnane:
Energy Efficient Elliptic Curve Processor. PATMOS 2008: 287-296 - 2007
- [j1]Maurice Keller, Robert Ronan, William P. Marnane, Colin C. Murphy:
Hardware architectures for the Tate pairing over GF(2m). Comput. Electr. Eng. 33(5-6): 392-406 (2007) - [c4]Maurice Keller, William P. Marnane:
Low Power Elliptic Curve Cryptography. PATMOS 2007: 310-319 - 2006
- [c3]Maurice Keller, Tim Kerins, Francis M. Crowe, William P. Marnane:
FPGA Implementation of a GF(2m) Tate Pairing Architecture. ARC 2006: 358-369 - [c2]Maurice Keller, Robert Ronan, William P. Marnane, Colin C. Murphy:
A GF(24m) Inverter and its Application in a Reconfigurable Tate Pairing Processor. ReConFig 2006: 158-167 - 2005
- [c1]Maurice Keller, Tim Kerins, William P. Marnane:
FPGA Implementation of a GF(24M) Multiplier for use in Pairing Based Cryptosystems. FPL 2005: 594-597
Coauthor Index
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