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2000 – 2009
- 2005
[c7]Christian Haubelt, Marek Jersak, Kai Richter, Karsten Strehl, Dirk Ziegenbein, Rolf Ernst, Jürgen Teich, Lothar Thiele:
SPI-Workbench - Modellierung, Analyse und Optimierung eingebetteter Systeme. GI Jahrestagung (2) 2005: 693-697- 2001
- [j3]Karsten Strehl, Lothar Thiele, Matthias Gries
, Dirk Ziegenbein, Rolf Ernst, Jürgen Teich:
FunState-an internal design representation for codesign. IEEE Trans. Very Large Scale Integr. Syst. 9(4): 524-544 (2001) - 2000
- [b1]Karsten Strehl:
Symbolic methods applied to formal verification and synthesis in embedded systems design. ETH Zurich, Zürich, Switzerland, Shaker 2000, ISBN 978-3-8265-7193-0, pp. 1-158 - [j2]Lothar Thiele, Jürgen Teich, Karsten Strehl:
Regular state machines. Parallel Algorithms Appl. 15(3-4): 265-300 (2000) - [j1]Karsten Strehl, Lothar Thiele:
Interval diagrams for efficient symbolic verification of processnetworks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(8): 939-956 (2000) - [c6]Karsten Strehl, Claudio Moraga, Karl-Heinz Temme, Radomir S. Stankovic:
Fuzzy Decision Diagrams for the Representation, Analysis and Optimization of Rule Bases. ISMVL 2000: 127-132
1990 – 1999
- 1999
- [c5]Karsten Strehl, Lothar Thiele, Dirk Ziegenbein, Rolf Ernst, Jürgen Teich:
Scheduling hardware/software systems using symbolic techniques. CODES 1999: 173-177 - [c4]Karsten Strehl, Lothar Thiele:
Interval Diagram Techniques for Symbolic Model Checking of Petri Nets. DATE 1999: 756-757 - [c3]Lothar Thiele, Karsten Strehl, Dirk Ziegenbein, Rolf Ernst, Jürgen Teich:
FunState - an internal design representation for codesign. ICCAD 1999: 558-565 - [c2]Karsten Strehl:
Interval Diagrams: Increasing Efficiency of Symbolic Real-Time Verification. RTCSA 1999: 488- - 1998
- [c1]Karsten Strehl, Lothar Thiele:
Symbolic model checking of process networks using interval diagram techniques. ICCAD 1998: 686-692
Coauthor Index
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