"Generating Architecture-Level Abstractions from RTL Designs for Processors ..."

Yu Zeng et al. (2021)

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DOI: 10.1109/ICCAD51958.2021.9643584

access: closed

type: Conference or Workshop Paper

metadata version: 2023-09-30

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Yu Zeng, Bo-Yuan Huang, Hongce Zhang, Aarti Gupta, Sharad Malik:
Generating Architecture-Level Abstractions from RTL Designs for Processors and Accelerators Part I: Determining Architectural State Variables. ICCAD 2021: 1-9

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