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Po-Chun Chien

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2020 – today

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2024
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Dirk Beyer, Po-Chun Chien, Marek Jankola, Nian-Ze Lee:
A Transferability Study of Interpolation-Based Hardware Model Checking for Software Verification. Proc. ACM Softw. Eng. 1(FSE): 2028-2050 (2024)
[c11]
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  - conf/fm/BaierBCJJKLLRWW24
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Daniel Baier, Dirk Beyer, Po-Chun Chien, Marie-Christine Jakobs, Marek Jankola, Matthias Kettl, Nian-Ze Lee, Thomas Lemberger, Marian Lingsch Rosenfeld, Henrik Wachowitz, Philipp Wendler:
Software Verification with CPAchecker 3.0: Tutorial and User Guide. FM (2) 2024: 543-570
[c10]
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Dirk Beyer, Po-Chun Chien, Nian-Ze Lee:
Augmenting Interpolation-Based Model Checking with Auxiliary Invariants. SPIN 2024: 227-247
[c9]
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Zsófia Ádám, Dirk Beyer, Po-Chun Chien, Nian-Ze Lee, Nils Sirrenberg:
Btor2-Cert: A Certifying Hardware-Verification Framework Using Software Analyzers. TACAS (3) 2024: 129-149
[c8]
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Daniel Baier, Dirk Beyer, Po-Chun Chien, Marek Jankola, Matthias Kettl, Nian-Ze Lee, Thomas Lemberger, Marian Lingsch Rosenfeld, Martin Spiessl, Henrik Wachowitz, Philipp Wendler:
CPAchecker 2.3 with Strategy Selection - (Competition Contribution). TACAS (3) 2024: 359-364
[c7]
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Po-Chun Chien, Nian-Ze Lee:
CPV: A Circuit-Based Program Verifier. TACAS (3) 2024: 365-370
[i4]
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  - journals/corr/abs-2403-07821
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Dirk Beyer, Po-Chun Chien, Nian-Ze Lee:
Augmenting Interpolation-Based Model Checking with Auxiliary Invariants (Extended Version). CoRR abs/2403.07821 (2024)
[i3]
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  - journals/corr/abs-2407-15551
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Salih Ates, Dirk Beyer, Po-Chun Chien, Nian-Ze Lee:
MoXIchecker: An Extensible Model Checker for MoXI. CoRR abs/2407.15551 (2024)
[i2]
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  - journals/corr/abs-2409-02094
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Daniel Baier, Dirk Beyer, Po-Chun Chien, Marie-Christine Jakobs, Marek Jankola, Matthias Kettl, Nian-Ze Lee, Thomas Lemberger, Marian Lingsch Rosenfeld, Henrik Wachowitz, Philipp Wendler:
Software Verification with CPAchecker 3.0: Tutorial and User Guide (Extended Version). CoRR abs/2409.02094 (2024)
2023
[c6]
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  - conf/kbse/BeyerCL23
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Dirk Beyer, Po-Chun Chien, Nian-Ze Lee:
CPA-DF: A Tool for Configurable Interval Analysis to Boost Program Verification. ASE 2023: 2050-2053
[c5]
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Dirk Beyer, Po-Chun Chien, Nian-Ze Lee:
Bridging Hardware and Software Analysis with Btor2C: A Word-Level-Circuit-to-C Translator. TACAS (2) 2023: 152-172
[d7]
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Zsófia Ádám, Dirk Beyer, Po-Chun Chien, Nian-Ze Lee, Nils Sirrenberg:
Reproduction Package for TACAS 2024 Submission 'Btor2-Cert: A Certifying Hardware-Verification Framework Using Software Analyzers'. Zenodo, 2023
[d6]
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Dirk Beyer, Po-Chun Chien, Nian-Ze Lee:
Reproduction Package for ASE 2023 Tool-Demo Submission 'CPA-DF: A Tool for Configurable Interval Analysis to Boost Program Verification'. Version ASE23-submission. Zenodo, 2023 [all versions]
[d5]
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Dirk Beyer, Po-Chun Chien, Nian-Ze Lee:
Reproduction Package for ASE 2023 Article 'CPA-DF: A Tool for Configurable Interval Analysis to Boost Program Verification'. Version ASE23-proceedings. Zenodo, 2023 [all versions]
[d4]
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Dirk Beyer, Po-Chun Chien, Nian-Ze Lee:
SoSy-Lab Virtual Machine (Ubuntu 22.04 LTS). Version 22.04. Zenodo, 2023 [all versions]
[d3]
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  - data/10/BeyerCL23c
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Dirk Beyer, Po-Chun Chien, Nian-Ze Lee:
Reproduction package for VMCAI 2024 submission 'Augmenting Interpolation-Based Model Checking with Auxiliary Invariants'. Zenodo, 2023
[d2]
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Dirk Beyer, Nian-Ze Lee, Po-Chun Chien:
Reproduction Package for TACAS 2023 Article 'Bridging Hardware and Software Analysis with Btor2C: A Word-Level-Circuit-to-C Converter'. Version Btor2C-artifact-TACAS23-proceedings. Zenodo, 2023 [all versions]
2022
[d1]
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Dirk Beyer, Nian-Ze Lee, Po-Chun Chien:
Reproduction Package for TACAS 2023 Submission 'Bridging Hardware and Software Analysis with Btor2C: A Word-Level-Circuit-to-C Converter'. Version Btor2C-artifact-TACAS23-submission. Zenodo, 2022 [all versions]
2021
[c4]
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  - conf/date/RaiNMZYYFMPRABC21
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Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa, Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. Abreu, Isac de Souza Campos, Augusto Andre Souza Berndt, Cristina Meinhardt, Jônata Tyska Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee:
Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. DATE 2021: 1026-1031
[c3]
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  - conf/iccad/WangLCWWLJH21
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Yu-Neng Wang, Yun-Rong Luo, Po-Chun Chien, Ping-Lun Wang, Hao-Ren Wang, Wan-Hsuan Lin, Jie-Hong Roland Jiang, Chung-Yang (Ric) Huang:
Compatible Equivalence Checking of X-Valued Circuits. ICCAD 2021: 1-9
2020
[c2]
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  - conf/dac/ChienJ20
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Po-Chun Chien, Jie-Hong R. Jiang:
Time Multiplexing via Circuit Folding. DAC 2020: 1-6
[i1]
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  - journals/corr/abs-2012-02530
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Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa Jr., Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. Abreu, Isac de Souza Campos, Augusto Andre Souza Berndt, Cristina Meinhardt, Jônata Tyska Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee:
Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. CoRR abs/2012.02530 (2020)

2010 – 2019

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2019
[c1]
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Po-Chun Chien, Jie-Hong R. Jiang:
Time-Frame Folding: Back to the Sequentiality. ICCAD 2019: 1-8

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