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2020 – today
- 2024
[j11]Ke Wu
, Kaizhao Zhang, Zhiwei Zhang, Muer Tie, Shanshuai Yuan, Jieru Zhao, Zhongxue Gan, Wenchao Ding:
HGS-Mapping: Online Dense Mapping Using Hybrid Gaussian Representation in Urban Scenes. IEEE Robotics Autom. Lett. 9(11): 9573-9580 (2024)- [j10]Yu Feng, Weikai Lin, Zihan Liu, Jingwen Leng, Minyi Guo, Han Zhao, Xiaofeng Hou, Jieru Zhao, Yuhao Zhu:
Potamoi: Accelerating Neural Rendering via a Unified Streaming Architecture. ACM Trans. Archit. Code Optim. 21(4): 80:1-80:25 (2024) - [j9]Tingyuan Liang, Gengjie Chen, Jieru Zhao, Sharad Sinha, Wei Zhang:
AMF-Placer 2.0: Open-Source Timing-Driven Analytical Mixed-Size Placer for Large-Scale Heterogeneous FPGA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(9): 2769-2782 (2024) - [j8]Jieru Zhao, Pai Zeng, Guan Shen, Quan Chen, Minyi Guo:
Hardware-Software Co-Design Enabling Static and Dynamic Sparse Attention Mechanisms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(9): 2783-2796 (2024) - [j7]Jieru Zhao, Guan Shen, Wenchao Ding, Quan Chen, Minyi Guo:
Automatic Mapping of Heterogeneous DNN Models on Adaptive Multiaccelerator Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(12): 4701-4714 (2024) - [j6]Linfeng Du, Tingyuan Liang, Xiaofeng Zhou, Jinming Ge, Shangkun Li, Sharad Sinha, Jieru Zhao, Zhiyao Xie, Wei Zhang:
FADO: Floorplan-Aware Directive Optimization Based on Synthesis and Analytical Models for High-Level Synthesis Designs on Multi-Die FPGAs. ACM Trans. Reconfigurable Technol. Syst. 17(3): 47:1-47:33 (2024) - [j5]Yuqi Li, Kehao Zhao, Jieru Zhao, Qirui Wang, Shuda Zhong, Nageswara Lalam, Ruishu F. Wright, Peipei Zhou, Kevin P. Chen:
FiberFlex: Real-time FPGA-based Intelligent and Distributed Fiber Sensor System for Pedestrian Recognition. ACM Trans. Reconfigurable Technol. Syst. 17(4): 57:1-57:30 (2024) - [c28]Ke Wu, Kaizhao Zhang, Mingzhe Gao, Jieru Zhao, Zhongxue Gan, Wenchao Ding:
Swift-Mapping: Online Neural Implicit Dense Mapping in Urban Scenes. AAAI 2024: 6048-6056 - [c27]Mingzhe Gao, Jieru Zhao, Zhe Lin, Minyi Guo:
Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNs. DATE 2024: 1-6 - [c26]Muer Tie, Julong Wei, Ke Wu, Zhengjun Wang, Shanshuai Yuan, Kaizhao Zhang, Jie Jia, Jieru Zhao, Zhongxue Gan, Wenchao Ding:
O 2V-Mapping: Online Open-Vocabulary Mapping with Neural Implicit Representation. ECCV (87) 2024: 318-333 - [c25]Weichuang Zhang, Jieru Zhao, Guan Shen, Quan Chen, Chen Chen, Minyi Guo:
An Optimizing Framework on MLIR for Efficient FPGA-based Accelerator Generation. HPCA 2024: 75-90 - [c24]Mingzhe Gao, Jieru Zhao, Zhe Lin, Wenchao Ding, Xiaofeng Hou, Yu Feng, Chao Li, Minyi Guo:
AutoVCoder: A Systematic Framework for Automated Verilog Code Generation using LLMs. ICCD 2024: 162-169 - [c23]Xiaofeng Hou, Tongqiao Xu, Chao Li, Cheng Xu, Jiacheng Liu, Yang Hu, Jieru Zhao, Jingwen Leng, Kwang-Ting Cheng, Minyi Guo:
A Tale of Two Domains: Exploring Efficient Architecture Design for Truly Autonomous Things. ISCA 2024: 167-181 - [c22]Zuo Gan, Chen Chen, Jiayi Zhang, Gaoxiong Zeng, Yifei Zhu, Jieru Zhao, Quan Chen, Minyi Guo:
PAS: Towards Accurate and Efficient Federated Learning with Parameter-Adaptive Synchronization. IWQoS 2024: 1-10 - [i21]Weichuang Zhang, Jieru Zhao, Guan Shen, Quan Chen, Chen Chen, Minyi Guo:
An Optimizing Framework on MLIR for Efficient FPGA-based Accelerator Generation. CoRR abs/2401.05154 (2024) - [i20]Mingzhe Gao, Jieru Zhao, Zhe Lin, Minyi Guo:
Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNs. CoRR abs/2401.08696 (2024) - [i19]Ke Wu, Kaizhao Zhang, Zhiwei Zhang, Shanshuai Yuan, Muer Tie, Julong Wei, Zijun Xu, Jieru Zhao, Zhongxue Gan, Wenchao Ding:
HGS-Mapping: Online Dense Mapping Using Hybrid Gaussian Representation in Urban Scenes. CoRR abs/2403.20159 (2024) - [i18]Muer Tie, Julong Wei, Zhengjun Wang, Ke Wu, Shansuai Yuan, Kaizhao Zhang, Jie Jia, Jieru Zhao, Zhongxue Gan, Wenchao Ding:
O2V-Mapping: Online Open-Vocabulary Mapping with Neural Implicit Representation. CoRR abs/2404.06836 (2024) - [i17]Pai Zeng, Zhenyu Ning, Jieru Zhao, Weihao Cui, Mengwei Xu, Liwei Guo, Xusheng Chen, Yizhou Shan:
The CAP Principle for LLM Serving: A Survey of Long-Context Large Language Model Serving. CoRR abs/2405.11299 (2024) - [i16]Mingzhe Gao, Jieru Zhao, Zhe Lin, Wenchao Ding, Xiaofeng Hou, Yu Feng, Chao Li, Minyi Guo:
AutoVCoder: A Systematic Framework for Automated Verilog Code Generation using LLMs. CoRR abs/2407.18333 (2024) - [i15]Yu Feng, Weikai Lin, Zihan Liu, Jingwen Leng, Minyi Guo, Han Zhao, Xiaofeng Hou, Jieru Zhao, Yuhao Zhu:
Potamoi: Accelerating Neural Rendering via a Unified Streaming Architecture. CoRR abs/2408.06608 (2024) - [i14]Zhenyu Ning, Jieru Zhao, Qihao Jin, Wenchao Ding, Minyi Guo:
Inf-MLLM: Efficient Streaming Inference of Multimodal Large Language Models on a Single GPU. CoRR abs/2409.09086 (2024) - [i13]Zijun Xu, Rui Jin, Ke Wu, Yi Zhao, Zhiwei Zhang, Jieru Zhao, Fei Gao, Zhongxue Gan, Wenchao Ding:
HGS-Planner: Hierarchical Planning Framework for Active Scene Reconstruction Using 3D Gaussian Splatting. CoRR abs/2409.17624 (2024) - [i12]Kunyun Wang, Jieru Zhao, Shuo Yang, Wenchao Ding, Minyi Guo:
SparseTem: Boosting the Efficiency of CNN-Based Video Encoders by Exploiting Temporal Continuity. CoRR abs/2410.20790 (2024) - [i11]Jie Zhang, Hongjing Huang, Xuzheng Xu, Xiang Li, Jieru Zhao, Ming Liu, Zeke Wang:
RPCAcc: A High-Performance and Reconfigurable PCIe-attached RPC Accelerator. CoRR abs/2411.07632 (2024) - [i10]Guangda Liu, Chengwei Li, Jieru Zhao, Chenqi Zhang, Minyi Guo:
ClusterKV: Manipulating LLM KV Cache in Semantic Space for Recallable Compression. CoRR abs/2412.03213 (2024) - 2023
- [j4]Jinyang Guo, Lu Zhang, José Romero Hung, Chao Li, Jieru Zhao, Minyi Guo:
FPGA sharing in the cloud: a comprehensive analysis. Frontiers Comput. Sci. 17(5): 175106 (2023) - [j3]Zhe Lin, Tingyuan Liang, Jieru Zhao, Sharad Sinha, Wei Zhang:
HL-Pow: Learning-Assisted Pre-RTL Power Modeling and Optimization for FPGA HLS. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(11): 3925-3938 (2023) - [c21]Zijun Li, Chuhao Xu, Quan Chen, Jieru Zhao, Chen Chen, Minyi Guo:
DataFlower: Exploiting the Data-flow Paradigm for Serverless Workflow Orchestration. ASPLOS (4) 2023: 57-72 - [c20]Guan Shen, Jieru Zhao, Zeke Wang, Zhe Lin, Wenchao Ding, Chentao Wu, Quan Chen, Minyi Guo:
MARS: Exploiting Multi-Level Parallelism for DNN Workloads on Adaptive Multi-Accelerator Systems. DAC 2023: 1-6 - [c19]Tao Yang, Yiyuan Zhou, Qidong Tang, Feng Xu, Hui Ma, Jieru Zhao, Li Jiang:
SpMMPlu: A Compiler Plug-in with Sparse IR for Efficient Sparse Matrix Multiplication. DAC 2023: 1-6 - [c18]Qi Liu, Mo Sun, Jie Sun, Liqiang Lu, Jieru Zhao, Zeke Wang:
SSiMD: Supporting Six Signed Multiplications in a DSP Block for Low-Precision CNN on FPGAs. ICFPT 2023: 161-169 - [c17]Cunchen Hu, Chenxi Wang, Sa Wang, Ninghui Sun, Yungang Bao, Jieru Zhao, Sanidhya Kashyap, Pengfei Zuo, Xusheng Chen, Liangliang Xu, Qin Zhang, Hao Feng, Yizhou Shan:
Skadi: Building a Distributed Runtime for Data Systems in Disaggregated Data Centers. HotOS 2023: 94-102 - [c16]Wenchao Ding, Jieru Zhao, Yubin Chu, Haihui Huang, Tong Qin, Chunjing Xu, Yuxiang Guan, Zhongxue Gan:
FlowMap: Path Generation for Automated Vehicles in Open Space Using Traffic Flow. ICRA 2023: 1616-1622 - [c15]Pu Pang, Yaoxuan Li, Bo Liu, Quan Chen, Zhou Yu, Zhibin Yu, Deze Zeng, Jingwen Leng, Jieru Zhao, Minyi Guo:
PAC: Preference-Aware Co-location Scheduling on Heterogeneous NUMA Architectures To Improve Resource Utilization. ICS 2023: 75-86 - [i9]Zijun Li, Chuhao Xu, Quan Chen, Jieru Zhao, Chen Chen, Minyi Guo:
DataFlower: Exploiting the Data-flow Paradigm for Serverless Workflow Orchestration. CoRR abs/2304.14629 (2023) - [i8]Wenchao Ding, Jieru Zhao, Yubin Chu, Haihui Huang, Tong Qin, Chunjing Xu, Yuxiang Guan, Zhongxue Gan:
FlowMap: Path Generation for Automated Vehicles in Open Space Using Traffic Flow. CoRR abs/2305.01622 (2023) - [i7]Guan Shen, Jieru Zhao, Zeke Wang, Zhe Lin, Wenchao Ding, Chentao Wu, Quan Chen, Minyi Guo:
MARS: Exploiting Multi-Level Parallelism for DNN Workloads on Adaptive Multi-Accelerator Systems. CoRR abs/2307.12234 (2023) - 2022
- [c14]Jiuchen Shi, Kaihua Fu, Quan Chen, Changpeng Yang, Pengfei Huang, Mosong Zhou, Jieru Zhao, Chen Chen, Minyi Guo:
Characterizing and orchestrating VM reservation in geo-distributed clouds to improve the resource efficiency. SoCC 2022: 94-109 - [c13]Guan Shen, Jieru Zhao, Quan Chen, Jingwen Leng, Chao Li, Minyi Guo:
SALO: an efficient spatial accelerator enabling hybrid sparse attention mechanisms for long sequences. DAC 2022: 571-576 - [c12]Zhe Lin, Zike Yuan, Jieru Zhao, Wei Zhang, Hui Wang, Yonghong Tian:
PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs. DATE 2022: 1341-1346 - [c11]Haowei Huang, Pu Pang, Quan Chen, Jieru Zhao, Wenli Zheng, Minyi Guo:
CSC: Collaborative System Configuration for I/O-Intensive Applications in Multi-Tenant Clouds. IPDPS 2022: 1327-1337 - [i6]Zhe Lin, Zike Yuan, Jieru Zhao, Wei Zhang, Hui Wang, Yonghong Tian:
PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs. CoRR abs/2201.10114 (2022) - [i5]Guan Shen, Jieru Zhao, Quan Chen, Jingwen Leng, Chao Li, Minyi Guo:
SALO: An Efficient Spatial Accelerator Enabling Hybrid Sparse Attention Mechanisms for Long Sequences. CoRR abs/2206.14550 (2022) - [i4]Tingyuan Liang, Gengjie Chen, Jieru Zhao, Sharad Sinha, Wei Zhang:
AMF-Placer 2.0: Open Source Timing-driven Analytical Mixed-size Placer for Large-scale Heterogeneous FPGA. CoRR abs/2210.08682 (2022) - 2021
- [c10]Tingyuan Liang, Gengjie Chen, Jieru Zhao, Sharad Sinha, Wei Zhang:
AMF-Placer: High-Performance Analytical Mixed-size Placer for FPGA. ICCAD 2021: 1-9 - [c9]Han Zhao, Weihao Cui, Quan Chen, Jieru Zhao, Jingwen Leng, Minyi Guo:
Exploiting Intra-SM Parallelism in GPUs via Persistent and Elastic Blocks. ICCD 2021: 290-298 - [c8]Weihao Cui, Han Zhao, Quan Chen, Ningxin Zheng, Jingwen Leng, Jieru Zhao, Zhuo Song, Tao Ma, Yong Yang, Chao Li, Minyi Guo:
Enable simultaneous DNN services based on deterministic operator overlap and precise latency prediction. SC 2021: 15 - 2020
- [j2]Jieru Zhao, Liang Feng, Sharad Sinha, Wei Zhang, Yun Liang, Bingsheng He:
Performance Modeling and Directives Optimization for High-Level Synthesis on FPGA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(7): 1428-1441 (2020) - [c7]Zhe Lin, Jieru Zhao, Sharad Sinha, Wei Zhang:
HL-Pow: A Learning-Based Power Modeling Framework for High-Level Synthesis. ASP-DAC 2020: 574-580 - [c6]Jieru Zhao, Tingyuan Liang, Liang Feng, Wenchao Ding, Sharad Sinha, Wei Zhang, Shaojie Shen:
FP-Stereo: Hardware-Efficient Stereo Vision for Embedded Applications. FPL 2020: 269-276 - [i3]Jieru Zhao, Tingyuan Liang, Liang Feng, Wenchao Ding, Sharad Sinha, Wei Zhang, Shaojie Shen:
FP-Stereo: Hardware-Efficient Stereo Vision for Embedded Applications. CoRR abs/2006.03250 (2020) - [i2]Zhe Lin, Jieru Zhao, Sharad Sinha, Wei Zhang:
HL-Pow: A Learning-Based Power Modeling Framework for High-Level Synthesis. CoRR abs/2009.00871 (2020)
2010 – 2019
- 2019
- [c5]Liang Feng, Jieru Zhao, Tingyuan Liang, Sharad Sinha, Wei Zhang:
LAMA: Link-Aware Hybrid Management for Memory Accesses in Emerging CPU-FPGA Platforms. DAC 2019: 1 - [c4]Jieru Zhao, Tingyuan Liang, Sharad Sinha, Wei Zhang:
Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis. DATE 2019: 1130-1135 - [c3]Liang Feng, Jieru Zhao, Tingyuan Liang, Sharad Sinha, Wei Zhang:
A Hybrid Data-Consistent Framework for Link-Aware AccessManagement in Emerging CPU-FPGA Platforms. FPGA 2019: 188 - [c2]Tingyuan Liang, Jieru Zhao, Liang Feng, Sharad Sinha, Wei Zhang:
Hi-ClockFlow: Multi-Clock Dataflow Automation and Throughput Optimization in High-Level Synthesis. ICCAD 2019: 1-6 - [i1]Jieru Zhao, Tingyuan Liang, Sharad Sinha, Wei Zhang:
Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis. CoRR abs/1905.03852 (2019) - 2018
- [j1]Tingyuan Liang, Jieru Zhao, Liang Feng, Sharad Sinha, Wei Zhang:
Hi-DMM: High-Performance Dynamic Memory Management in High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(11): 2555-2566 (2018) - 2017
- [c1]Jieru Zhao, Liang Feng, Sharad Sinha, Wei Zhang, Yun Liang, Bingsheng He:
COMBA: A comprehensive model-based analysis framework for high level synthesis of real applications. ICCAD 2017: 430-437
Coauthor Index
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