default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID30th FPL 2020: Gothenburg, Sweden
- Nele Mentens, Leonel Sousa, Pedro Trancoso, Miquel Pericàs, Ioannis Sourdis:
30th International Conference on Field-Programmable Logic and Applications, FPL 2020, Gothenburg, Sweden, August 31 - September 4, 2020. IEEE 2020, ISBN 978-1-7281-9902-3
Session F1: Architecture
- Kaan Kara, Christoph Hagleitner, Dionysios Diamantopoulos, Dimitris Syrivelis, Gustavo Alonso:
High Bandwidth Memory on FPGAs: A Data Analytics Perspective. 1-8 - Gagandeep Singh, Dionysios Diamantopoulos, Christoph Hagleitner, Juan Gómez-Luna, Sander Stuijk
, Onur Mutlu, Henk Corporaal:
NERO: A Near High-Bandwidth Memory Stencil Accelerator for Weather Prediction Modeling. 9-17 - Gurshaant Malik, Ian Elmor Lang, Rodolfo Pellizzoni, Nachiket Kapre:
Learn the Switches: Evolving FPGA NoCs with Stall-Free and Backpressure Based Routers. 18-25 - Emre Karabulut, Aydin Aysu:
RANTT: A RISC-V Architecture Extension for the Number Theoretic Transform. 26-32 - Guilherme Korol, Michael Guilherme Jordan, Marcelo Brandalero, Michael Hübner, Mateus Beck Rutzig, Antonio Carlos Schneider Beck:
MCEA: A Resource-Aware Multicore CGRA Architecture for the Edge. 33-39 - João Paulo Cardoso de Lima, Marcelo Brandalero, Luigi Carro:
Endurance-Aware RRAM-Based Reconfigurable Architecture using TCAM Arrays. 40-46
Session F2: Applications
- Amit Kulkarni, Monica Chiosa, Thomas B. Preußer, Kaan Kara, David Sidler, Gustavo Alonso:
HyperLogLog Sketch Acceleration on FPGA. 47-56 - Abbas Haghi, Lluc Alvarez, Jordà Polo, Dionysios Diamantopoulos, Christoph Hagleitner, Miquel Moretó:
A Hardware/Software Co-Design of K-mer Counting Using a CAPI-Enabled FPGA. 57-64 - Philippos Papaphilippou, Chris Brooks, Wayne Luk:
An Adaptable High-Throughput FPGA Merge Sorter for Accelerating Database Analytics. 65-72
Session S1: Architecture
- Satoshi Mitsuno, Junichiro Kadomoto, Toru Koizumi, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai:
A High-Performance Out-of-Order Soft Processor Without Register Renaming. 73-78 - Kati Tervo, Samawat Malik, Topi Leppänen, Pekka Jääskeläinen:
TTA-SIMD Soft Core Processors. 79-84 - Nikolaos Charalampos Papadopoulos, Vasileios Karakostas, Konstantinos Nikas, Nectarios Koziris, Dionisios N. Pnevmatikatos:
A Configurable TLB Hierarchy for the RISC-V Architecture. 85-90 - Joseph Melber, James C. Hoe:
A Service-Oriented Memory Architecture for FPGA Computing. 91-97
Session S2: Applications
- Linjun Qiao, Guojie Luo, Wentai Zhang, Ming Jiang:
FPGA Acceleration of Ray-Based Iterative Algorithm for 3D Low-Dose CT Reconstruction. 98-102 - Naoki Fujieda:
On the Feasibility of TERO-Based True Random Number Generator on Xilinx FPGAs. 103-108 - Shashwat Khandelwal, Ziaul Choudhury, Shashwat Shrivastava, Suresh Purini:
Accelerating Local Laplacian Filters on FPGAs. 109-114 - Julien Mazuet, Michel Narozny, Catherine Dezan, Jean-Philippe Diguet:
A Seamless DFT/FFT Self-Adaptive Architecture for Embedded Radar Applications. 115-120 - Thomas B. Preußer, Monica Chiosa, Alexander Weiss, Gustavo Alonso:
Using DSP Slices as Content-Addressable Update Queues. 121-126 - Abhishek Kumar Jain, Hossein Omidian, Henri Fraisse, Mansimran Benipal, Lisa Liu, Dinesh Gaitonde:
A Domain-Specific Architecture for Accelerating Sparse Matrix Vector Multiplication on FPGAs. 127-132 - Atharva Gondhalekar, Wu-Chun Feng:
Exploring FPGA Optimizations in OpenCL for Breadth-First Search on Sparse Graph Datasets. 133-137
Session F3: Synthesis and Testing
- Dani Maarouf, Ahmed Shamli, Timothy Martin, Gary Gréwal, Shawki Areibi:
A Deep-Learning Framework for Predicting Congestion During FPGA Placement. 138-144 - Niansong Zhang, Xiang Chen, Nachiket Kapre:
RapidLayout: Fast Hard Block Placement of FPGA-Optimized Systolic Arrays using Evolutionary Algorithms. 145-152 - Stefan Nikolic, Grace Zgheib, Paolo Ienne:
Timing-Driven Placement for FPGA Architectures with Dedicated Routing Paths. 153-161 - Farah Abid, Darshana Jayasinghe, Sompasong Somsavaddy, Sri Parameswaran:
LFTSM: Lightweight and Fully Testable SEU Mitigation System for Xilinx Processor-Based SoCs. 162-168 - Tanner Gaskin, Hayden Cook, Wesley Stirk, Robert Lucas, Jeffrey Goeders, Brad L. Hutchings:
Using Novel Configuration Techniques for Accelerated FPGA Aging. 169-175
Session F4: Security
- Milad Bahadori, Kimmo Järvinen:
Compact and Programmable yet High-Performance SoC Architecture for Cryptographic Pairings. 176-184 - Dina G. Mahmoud, Wei Hu, Mirjana Stojilovic:
X-Attack: Remote Activation of Satisfiability Don't-Care Hardware Trojans on Shared FPGAs. 185-192 - Flora Coleman, Behnaz Rezvani, Sachin Sachin, William Diehl:
Side Channel Resistance at a Cost: A Comparison of ARX-Based Authenticated Encryption. 193-199 - Benjamin Hettwer, Kallyan Das, Sebastien Leger, Stefan Gehrer, Tim Güneysu:
Lightweight Side-Channel Protection using Dynamic Clock Randomization. 200-207
Session S3: Synthesis and Testing
- Ang Li, Ting-Jung Chang, David Wentzlaff:
Automated Design of FPGAs Facilitated by Cycle-Free Routing. 208-213 - Sajjad Rostami Sani, Farheen Fatima Khan, Anas Razzaq, Andy Gean Ye:
Measuring the Accuracy of Layout Area Estimation Models of Tile-Based FPGAs in FinFET Technology. 214-219 - Nadesh Ramanathan, George A. Constantinides, John Wickerson:
Precise Pointer Analysis in High-Level Synthesis. 220-224 - Kahlan Gibson, Esther Roorda, Daniel Holanda Noronha, Steven J. E. Wilton:
Syncopation: Adaptive Clock Management for High-Level Synthesis Generated Circuits on FPGAs. 225-230
Session S4: Security
- George Provelengios, Daniel E. Holcomb, Russell Tessier:
Power Wasting Circuits for Cloud FPGA Attacks. 231-235 - Pierre-Francois Wolfe, Rushi Patel, Robert Munafo, Mayank Varia, Martin C. Herbordt:
Secret Sharing MPC on FPGAs in the Datacenter. 236-242 - João Carlos Resende, Ricardo J. R. Maçãs, Ricardo Chaves:
Mask Scrambling Against SCA on Reconfigurable TBOX-Based AES. 243-248 - Wei Yan, Fatemeh Tehranipoor, Xuan Zhang, John A. Chandy:
FLASH: FPGA Locality-Aware Sensitive Hash for Nearest Neighbor Search and Clustering Application. 249-253
Session F5: AI, Vision & Robotics
- Tao Yang, Yunkun Liao, Jianping Shi, Yun Liang, Naifeng Jing, Li Jiang:
A Winograd-Based CNN Accelerator with a Fine-Grained Regular Sparsity Pattern. 254-261 - Duvindu Piyasena, Miyuru Thathsara, Sathursan Kanagarajah, Siew Kei Lam, Meiqing Wu:
Dynamically Growing Neural Network Architecture for Lifelong Deep Learning on the Edge. 262-268 - Jieru Zhao, Tingyuan Liang, Liang Feng, Wenchao Ding, Sharad Sinha, Wei Zhang, Shaojie Shen:
FP-Stereo: Hardware-Efficient Stereo Vision for Embedded Applications. 269-276 - Justin Knapheide, Benno Stabernack, Maximilian Kuhnke:
A High Throughput MobileNetV2 FPGA Implementation Based on a Flexible Architecture for Depthwise Separable Convolution. 277-283 - Yanqi Liu, Giuseppe Calderoni, Ruth Iris Bahar:
Hardware Acceleration of Monte-Carlo Sampling for Energy Efficient Robust Robot Manipulation. 284-290 - Yaman Umuroglu, Yash Akhauri, Nicholas James Fraser, Michaela Blott:
LogicNets: Co-Designed Neural Networks and Circuits for Extreme-Throughput Applications. 291-297
Session S5: AI, Vision & Robotics
- Ryosuke Kuramochi, Hiroki Nakahara:
An FPGA-Based Low-Latency Accelerator for Randomly Wired Neural Networks. 298-303 - Shashwat Shrivastava, Ziaul Choudhury, Shashwat Khandelwal, Suresh Purini:
FPGA Accelerator for Stereo Vision using Semi-Global Matching through Dependency Relaxation. 304-309 - Dionysios Diamantopoulos, Burkhard Ringlein, Mitra Purandare, Gagandeep Singh, Christoph Hagleitner:
Agile Autotuning of a Transprecision Tensor Accelerator Overlay for TVM Compiler Stack. 310-316 - Diederik Adriaan Vink, Aditya Rajagopal, Stylianos I. Venieris, Christos-Savvas Bouganis:
Caffe Barista: Brewing Caffe with FPGAs in the Training Loop. 317-322
Session S6: Tools, Technology, and Other
- Ryusuke Nebashi, Naoki Banno, Makoto Miyamura, Xu Bai, Kazunori Funahashi, Koichiro Okamoto, Noriyuki Iguchi, Hideaki Numata, Tadahiko Sugibayashi, Toshitsugu Sakamoto, Munehiro Tada:
A 171k-LUT Nonvolatile FPGA using Cu Atom-Switch Technology in 28nm CMOS. 323-327 - Marie Nguyen, Nathan Serafin, James C. Hoe:
Partial Reconfiguration for Design Optimization. 328-334 - Nick Brown:
Weighing Up the New Kid on the Block: Impressions of using Vitis for HPC Software Development. 335-340 - Richard Dorrance, Andrey Belogolovy, Hechen Wang, Xue Zhang:
A Digital Root Based Modular Reduction Technique for Power Efficient, Fault Tolerance in FPGAs. 341-346 - Ryan A. Cooke, Suhaib A. Fahmy:
Characterizing Latency Overheads in the Deployment of FPGA Accelerators. 347-352
PhD Forum
- Arjun Ramaswami, Tobias Kenter, Thomas D. Kühne, Christian Plessl:
Efficient Ab-Initio Molecular Dynamic Simulations by Offloading Fast Fourier Transformations to FPGAs. 353-354 - Gabriella D'Andrea, Luigi Pomante:
Design for ReConfigurability: An Electronic System Level Methodology to Exploit Reconfigurable Platforms. 355-356 - Cheolyong Bae, Oscar Gustafsson:
High-Speed Chromatic Dispersion Compensation Filtering in FPGAs for Coherent Optical Communication. 357-358 - Frans Skarman, Oscar Gustafsson, Daniel Jung, Mattias Krysander:
Acceleration of Simulation Models Through Automatic Conversion to FPGA Hardware. 359-360 - Tuan La, Kaspar Matas, Khoa Dang Pham, Dirk Koch:
Securing FPGA Accelerators at the Electrical Level for Multi-tenant Platforms. 361-362 - Kristiyan Manev, Dirk Koch:
Resource Elastic Database Acceleration. 363-364 - Kaspar Mätas, Dirk Koch:
Transparent Integration of a Dynamic FPGA Database Acceleration System. 365-366
Demo Night
- Nuno Paulino, João Canas Ferreira, João Bispo, João M. P. Cardoso:
Executing ARMv8 Loop Traces on Reconfigurable Accelerator via Binary Translation Framework. 367 - Khoa Dang Pham, Anuj Vaishnav, Joseph Powell, Dirk Koch:
A Self-Compilation Flow Demo on FOS - The FPGA Operating System. 368 - Tuan La, Kaspar Matas, Joseph Powell, Khoa Dang Pham, Dirk Koch:
Demo: A Closer Look at Malicious Bitstreams. 369 - Jaewon Lee, Hanning Chen, Jeffrey S. Young, Hyesoon Kim:
RISC-V FPGA Platform Toward ROS-Based Robotics Application. 370 - Erhan Baturay Onural, Ismail Emir Yuksel, Behzad Salami:
Demonstrating Reduced-Voltage FPGA-Based Neural Network Acceleration for Power-Efficiency. 371
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-11-20 21:08 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
