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ORCIDZiaul Choudhury
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2020 – today
- 2024
[i2]Shashwat Khandelwal, Ziaul Choudhury, Shashwat Shrivastava, Suresh Purini:
Accelerating local laplacian filters on FPGAs. CoRR abs/2402.12407 (2024)- 2023
- [j3]Ziaul Choudhury
, Anish Gulati, Suresh Purini:
FlowPix: Accelerating Image Processing Pipelines on an FPGA Overlay using a Domain Specific Compiler. ACM Trans. Archit. Code Optim. 20(4): 60:1-60:25 (2023) - 2022
- [j2]Ziaul Choudhury, Shashwat Shrivastava, Lavanya Ramapantulu, Suresh Purini:
An FPGA Overlay for CNN Inference with Fine-grained Flexible Parallelism. ACM Trans. Archit. Code Optim. 19(3): 34:1-34:26 (2022) - [j1]Biji George, Om Ji Omer, Ziaul Choudhury, Anoop V, Sreenivas Subramoney:
A Unified Programmable Edge Matrix Processor for Deep Neural Networks and Matrix Algebra. ACM Trans. Embed. Comput. Syst. 21(5): 63:1-63:30 (2022) - [c5]Shivani Maurya, Ziaul Choudhury, Suresh Purini:
Accuracy Configurable FPGA Implementation of Harris Corner Detection. ISVLSI 2022: 422-427 - 2020
- [c4]Suresh Purini, Vinamra Benara, Ziaul Choudhury, Uday Bondhugula:
Bitwidth customization in image processing pipelines using interval analysis and SMT solvers. CC 2020: 167-178 - [c3]Shashwat Khandelwal, Ziaul Choudhury, Shashwat Shrivastava, Suresh Purini:
Accelerating Local Laplacian Filters on FPGAs. FPL 2020: 109-114 - [c2]Shashwat Shrivastava, Ziaul Choudhury, Shashwat Khandelwal, Suresh Purini:
FPGA Accelerator for Stereo Vision using Semi-Global Matching through Dependency Relaxation. FPL 2020: 304-309
2010 – 2019
- 2018
- [i1]Vinamra Benara, Sahithi Rampalli, Ziaul Choudhury, Suresh Purini, Uday Bondhugula:
Synthesizing Power and Area Efficient Image Processing Pipelines on FPGAs using Customized Bit-widths. CoRR abs/1803.02660 (2018) - 2016
- [c1]Ziaul Choudhury, Suresh Purini, Shiva Rama Krishna:
A Hybrid CPU+GPU Working-Set Dictionary. ISPDC 2016: 56-63
Coauthor Index
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