"Synthesizing Power and Area Efficient Image Processing Pipelines on FPGAs ..."

Vinamra Benara et al. (2018)

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DOI: —

access: open

type: Informal or Other Publication

metadata version: 2018-08-13

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  - electronic edition @ arxiv.org (open access)
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  dblp key:
  - journals/corr/abs-1803-02660
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  persistent URL:
  - https://dblp.org/rec/journals/corr/abs-1803-02660
Vinamra Benara, Sahithi Rampalli, Ziaul Choudhury, Suresh Purini, Uday Bondhugula:
Synthesizing Power and Area Efficient Image Processing Pipelines on FPGAs using Customized Bit-widths. CoRR abs/1803.02660 (2018)

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