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ORCIDSajjad Rostami Sani
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2020 – today
- 2024
[j5]Sajjad Rostami Sani
, Andy Gean Ye:
Evaluating the Impact of Using Multiple-Metal Layers on the Layout Area of Switch Blocks for Tile-Based FPGAs in FinFET 7nm. ACM Trans. Reconfigurable Technol. Syst. 17(1): 17:1-17:29 (2024)- 2022
- [j4]Anas Razzaq, Sajjad Rostami Sani, Andy Gean Ye:
The effect of gate voltage boosting on the power efficiency of multi-context FPGAs. Integr. 86: 30-43 (2022) - [j3]Sajjad Rostami Sani, Andy Gean Ye:
Measuring the effect of track count and wire segment length on the layout area of switch blocks for tile-based FPGAs. Microprocess. Microsystems 92: 104563 (2022) - [c2]Sajjad Rostami Sani, Anas Razzaq, Andy Gean Ye:
Evaluating the impact of using multiple-metal layers on the layout area of switch blocks for tile-based FPGAs in FinFET 7nm. FCCM 2022: 1-9 - 2021
- [j2]Anas Razzaq, Sajjad Rostami Sani, Andy Gean Ye:
Designing efficient FPGA tiles for power-constrained ultra-low-power applications. Integr. 78: 124-134 (2021) - 2020
- [c1]Sajjad Rostami Sani, Farheen Fatima Khan, Anas Razzaq, Andy Gean Ye:
Measuring the Accuracy of Layout Area Estimation Models of Tile-Based FPGAs in FinFET Technology. FPL 2020: 214-219
2010 – 2019
- 2019
- [j1]Sajjad Rostami Sani, Mojtaba Valinataj, Saeideh Alinezhad Chamazcoti:
Parloom: A New Low-Power Set-Associative Instruction Cache Architecture Utilizing Enhanced Counting Bloom Filter and Partial Tags. J. Circuits Syst. Comput. 28(12): 1950203:1-1950203:25 (2019)
Coauthor Index
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