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ORCIDMojtaba Valinataj
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2020 – today
- 2023
[j12]Zahra Yazdanian Amiri, Mojtaba Valinataj
:
High-speed binary coded decimal digit multipliers with multiple error detection. Integr. 93: 102073 (2023)- 2022
- [j11]Mojtaba Valinataj, Axel Jantsch:
Hierarchical multipliers: A framework for high-speed multiple error detecting architectures. Microelectron. J. 125: 105459 (2022) - [c9]Roya Rahimi Disfani, Nima TaheriNejad, Mojtaba Valinataj:
Operational Conditions Analysis for Memristive Stateful Logics - A Study on IMPLY and TMSL. NEWCAS 2022: 480-484 - 2021
- [j10]Mojtaba Valinataj, Zahra Yazdanian Amiri:
Comments on "Improved designs of digit-by-digit decimal multiplier". Integr. 76: 135-138 (2021) - [j9]Maytham Allahi Rudposhti, Mojtaba Valinataj:
High-speed and low-cost carry select adders utilizing new optimized add-one circuit and multiplexer-based logic. Integr. 79: 61-72 (2021)
2010 – 2019
- 2019
- [j8]Sajjad Rostami Sani, Mojtaba Valinataj, Saeideh Alinezhad Chamazcoti:
Parloom: A New Low-Power Set-Associative Instruction Cache Architecture Utilizing Enhanced Counting Bloom Filter and Partial Tags. J. Circuits Syst. Comput. 28(12): 1950203:1-1950203:25 (2019) - 2018
- [j7]Hamid Jazayeriy, Sahar Bakhtar, Mojtaba Valinataj:
aPaRT: A Fast Meta-Heuristic Algorithm using Path-Relinking and Tabu Search for Allocating Machines to Operations in FJSP Problem. Inteligencia Artif. 21(61): 111-123 (2018) - [j6]Mojtaba Valinataj, Abbas Mohammadnezhad, Jari Nurmi:
A low-cost high-speed self-checking carry select adder with multiple-fault detection. Microelectron. J. 81: 16-27 (2018) - 2017
- [j5]Mojtaba Valinataj:
Novel parity-preserving reversible logic array multipliers. J. Supercomput. 73(11): 4843-4867 (2017) - 2016
- [j4]Mojtaba Valinataj, Mahboobeh Mirshekar, Hamid Jazayeri:
Novel low-cost and fault-tolerant reversible logic adders. Comput. Electr. Eng. 53: 56-72 (2016) - [j3]Mojtaba Valinataj, Mostafa Shahiri:
A low-cost, fault-tolerant and high-performance router architecture for on-chip networks. Microprocess. Microsystems 45: 151-163 (2016) - [c8]Mostafa Shahiri, Mojtaba Valinataj, Amir M. Rahmani:
A reliable and high-performance Network-on-Chip router through decoupled resource sharing. HPCS 2016: 88-95 - 2015
- [j2]Mojtaba Valinataj:
Fault-tolerant carry look-ahead adder architectures robust to multiple simultaneous errors. Microelectron. Reliab. 55(12): 2845-2857 (2015) - 2014
- [j1]Mojtaba Valinataj:
A novel self-checking carry lookahead adder with multiple error detection/correction. Microprocess. Microsystems 38(8): 1072-1081 (2014) - 2013
- [c7]Mojtaba Valinataj, Pasi Liljeberg, Juha Plosila:
Enhanced fault-tolerant Network-on-Chip architecture using hierarchical agents. DDECS 2013: 141-146 - 2011
- [c6]Mojtaba Valinataj:
Evaluation of Fault-Tolerant Routing Methods for NoC Architectures. DSD 2011: 446-449 - [c5]Mojtaba Valinataj, Pasi Liljeberg, Juha Plosila:
A fault-tolerant and hierarchical routing algorithm for NoC architectures. NORCHIP 2011: 1-6 - 2010
- [c4]Mojtaba Valinataj, Siamak Mohammadi, Juha Plosila, Pasi Liljeberg:
A fault-tolerant and congestion-aware routing algorithm for Networks-on-Chip. DDECS 2010: 139-144 - [c3]Mojtaba Valinataj, Siamak Mohammadi:
A fault-aware, reconfigurable and adaptive routing algorithm for NoC applications. VLSI-SoC 2010: 13-18
2000 – 2009
- 2008
- [c2]Mojtaba Valinataj, Siamak Mohammadi, Saeed Safari:
Inherent reliability evaluation of Networks-on-Chip based on analytical models. SoC 2008: 1-4 - 2007
- [c1]Mojtaba Valinataj, Saeed Safari:
Fault Tolerant Arithmetic Operations with Multiple Error Detection and Correction. DFT 2007: 188-196
Coauthor Index
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