default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDNachiket Kapre
Person information
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
showing all ?? records
2020 – today
- 2023
[c82]Zhuanhao Wu, Marat Bekmyrza, Nachiket Kapre, Hiren D. Patel:
Ditty: Directory-based Cache Coherence for Multicore Safety-critical Systems. DATE 2023: 1-6- 2022
- [j13]Niansong Zhang
, Xiang Chen, Nachiket Kapre:
RapidLayout: Fast Hard Block Placement of FPGA-optimized Systolic Arrays Using Evolutionary Algorithm. ACM Trans. Reconfigurable Technol. Syst. 15(4): 38:1-38:23 (2022) - [j12]Gurshaant Malik, Ian Elmor Lang, Rodolfo Pellizzoni, Nachiket Kapre:
HopliteML: Evolving Application Customized FPGA NoCs with Adaptable Routers and Regulators. ACM Trans. Reconfigurable Technol. Syst. 15(4): 40:1-40:33 (2022) - [c81]Srinirdheeshwar Kuttuva Prakash, Hiren D. Patel, Nachiket Kapre:
Managing HBM Bandwidth on Multi-Die FPGAs with FPGA Overlay NoCs. FCCM 2022: 1-9 - 2021
- [c80]Frederick Tombs, Alireza Mellat, Nachiket Kapre:
Mocarabe: High-Performance Time-Multiplexed Overlays for FPGAs. FCCM 2021: 115-123 - [c79]Ian Elmor Lang, Nachiket Kapre, Rodolfo Pellizzoni:
Worst-case latency analysis for the versal NoC network packet switch. NOCS 2021: 55-60 - 2020
- [j11]Tushar Garg, Saud Wasly, Rodolfo Pellizzoni, Nachiket Kapre:
HopliteBuf: Network Calculus-Based Design of FPGA NoCs with Provably Stall-Free FIFOs. ACM Trans. Reconfigurable Technol. Syst. 13(2): 6:1-6:35 (2020) - [c78]Ian Elmor Lang, Ziqiang Huang, Nachiket Kapre:
Exploring The Impact Of Switch Arity On Butterfly Fat Tree Fpga Nocs. FCCM 2020: 70-74 - [c77]Gurshaant Malik, Ian Elmor Lang, Rodolfo Pellizzoni, Nachiket Kapre:
Learn the Switches: Evolving FPGA NoCs with Stall-Free and Backpressure Based Routers. FPL 2020: 18-25 - [c76]Niansong Zhang, Xiang Chen, Nachiket Kapre:
RapidLayout: Fast Hard Block Placement of FPGA-Optimized Systolic Arrays using Evolutionary Algorithms. FPL 2020: 145-152 - [c75]Gurshaant Singh Malik, Lucian Petrica, Nachiket Kapre, Michaela Blott:
DarwiNN: efficient distributed neuroevolution under communication constraints. GECCO Companion 2020: 141-142 - [i2]Niansong Zhang, Xiang Chen, Nachiket Kapre:
RapidLayout: Fast Hard Block Placement of FPGA-optimized Systolic Arrays using Evolutionary Algorithms. CoRR abs/2002.06998 (2020)
2010 – 2019
- 2019
- [c74]Leo Liu, Jay Weng, Nachiket Kapre:
RapidRoute: Fast Assembly of Communication Structures for FPGA Overlays. FCCM 2019: 61-64 - [c73]Gurshaant Singh Malik, Nachiket Kapre:
Enhancing Butterfly Fat Tree NoCs for FPGAs with Lightweight Flow Control. FCCM 2019: 154-162 - [c72]Tushar Garg, Saud Wasly, Rodolfo Pellizzoni, Nachiket Kapre:
HopliteBuf: FPGA NoCs with Provably Stall-Free FIFOs. FPGA 2019: 222-231 - [c71]Gurshaant Singh Malik, Nachiket Kapre:
Enhancing Butterfly Fat Tree NoCs for FPGAs with Lightweight Flow Control. FPGA 2019: 308 - [c70]Leo Liu, Nachiket Kapre:
Timing-Aware Routing in the RapidWright Framework. FPL 2019: 24-30 - [c69]Ananda Samajdar, Tushar Garg, Tushar Krishna, Nachiket Kapre:
Scaling the Cascades: Interconnect-Aware FPGA Implementation of Machine Learning Problems. FPL 2019: 342-349 - [c68]Long Chung Chan, Gurshaant Malik, Nachiket Kapre:
Partitioning FPGA-Optimized Systolic Arrays for Fun and Profit. FPT 2019: 144-152 - 2018
- [j10]Gopalakrishna Hegde, Siddhartha, Nachiket Kapre:
CaffePresso: Accelerating Convolutional Networks on Embedded SoCs. ACM Trans. Embed. Comput. Syst. 17(1): 15:1-15:26 (2018) - [c67]Siddhartha, Nachiket Kapre:
Hoplite-Q: Priority-Aware Routing in FPGA Overlay NoCs. FCCM 2018: 17-24 - [c66]Asif Islam, Nachiket Kapre:
LegUp-NoC: High-Level Synthesis of Loops with Indirect Addressing. FCCM 2018: 117-124 - [c65]Nachiket Kapre, Tushar Krishna:
FastTrack: Exploiting Fast FPGA Wiring for Implementing NoC Shortcuts (Abstract Only). FPGA 2018: 286 - [c64]Benjamin Morcos, Terrence C. Stewart, Chris Eliasmith, Nachiket Kapre:
Implementing NEF Neural Networks on Embedded FPGAs. FPT 2018: 22-29 - [c63]Siddhartha, Nachiket Kapre:
DaCO: A High-Performance Token Dataflow Coprocessor Overlay for FPGAs. FPT 2018: 158-165 - [c62]Nachiket Kapre, Tushar Krishna:
FastTrack: Leveraging Heterogeneous FPGA Wires to Design Low-Cost High-Performance Soft NoCs. ISCA 2018: 739-751 - 2017
- [j9]Deheng Ye, Zhenchang Xing, Nachiket Kapre:
The structure and dynamics of knowledge network in domain-specific Q&A sites: a case study of stack overflow. Empir. Softw. Eng. 22(1): 375-406 (2017) - [j8]Nachiket Kapre, Jan Gray:
Hoplite: A Deflection-Routed Directional Torus NoC for FPGAs. ACM Trans. Reconfigurable Technol. Syst. 10(2): 14:1-14:24 (2017) - [c61]Siddhartha, Nachiket Kapre:
eBSP: Managing NoC traffic for BSP workloads on the 16-core Adapteva Epiphany-III processor. DATE 2017: 73-78 - [c60]Nachiket Kapre:
On Bit-Serial NoCs for FPGAs. FCCM 2017: 32-39 - [c59]Nachiket Kapre:
Implementing FPGA Overlay NoCs Using the Xilinx UltraScale Memory Cascades. FCCM 2017: 40-47 - [c58]Chethan Kumar H. B, Prashant Ravi, Gourav Modi, Nachiket Kapre:
120-core microAptiv MIPS Overlay for the Terasic DE5-NET FPGA board. FPGA 2017: 141-146 - [c57]Nachiket Kapre:
Deflection-routed butterfly fat trees on FPGAs. FPL 2017: 1-8 - [c56]Kizheppatt Vipin, Jan Gray, Nachiket Kapre:
Enabling partial reconfiguration and low latency routing using segmented FPGA NoCs. FPL 2017: 1-8 - [c55]Saud Wasly, Rodolfo Pellizzoni, Nachiket Kapre:
HopliteRT: An efficient FPGA NoC for real-time applications. FPT 2017: 64-71 - [c54]Nachiket Kapre, Hiren D. Patel:
Applying Models of Computation to OpenCL Pipes for FPGA Computing. IWOCL 2017: 9:1-9:4 - [i1]Siddhartha, Nachiket Kapre:
Out-of-Order Dataflow Scheduling for FPGA Overlays. CoRR abs/1705.02734 (2017) - 2016
- [j7]Nachiket Kapre:
Optimizing Soft Vector Processing in FPGA-Based Embedded Systems. ACM Trans. Reconfigurable Technol. Syst. 9(3): 17:1-17:17 (2016) - [c53]Gopalakrishna Hegde, Siddhartha, Nachiappan Ramasamy, Nachiket Kapre:
CaffePresso: an optimized library for deep learning on embedded accelerator-based platforms. CASES 2016: 14:1-14:10 - [c52]Prashant Ravi, Uma Syam, Nachiket Kapre:
Preventive Detection of Mosquito Populations using Embedded Machine Learning on Low Power IoT Platforms. ACM DEV 2016: 3:1-3:10 - [c51]Gopalakrishna Hegde, Siddhartha, Nachiappan Ramasamy, Vamsi Buddha, Nachiket Kapre:
Evaluating Embedded FPGA Accelerators for Deep Learning Applications. FCCM 2016: 25 - [c50]Nachiket Kapre, Siddhartha:
Communication Optimization for the 16-Core Epiphany Floating-Point Processor Array. FCCM 2016: 26 - [c49]Que Yanghua, Nachiket Kapre, Harnhua Ng, Kirvy Teo:
Improving Classification Accuracy of a Machine Learning Approach for FPGA Timing Closure. FCCM 2016: 80-83 - [c48]Nachiket Kapre:
Marathon: Statically-Scheduled Conflict-Free Routing on FPGA Overlay NoCs. FCCM 2016: 156-163 - [c47]Que Yanghua, Chinnakkannu Adaikkala Raj, Harnhua Ng, Kirvy Teo, Nachiket Kapre:
Case for Design-Specific Machine Learning in Timing Closure of FPGA Designs. FPGA 2016: 169-172 - [c46]Nachiket Kapre, Deheng Ye:
GPU-Accelerated High-Level Synthesis for Bitwidth Optimization of FPGA Datapaths. FPGA 2016: 185-194 - [c45]Li Ting, Harri Wijaya, Nachiket Kapre:
Machine-Learning driven Auto-Tuning of High-Level Synthesis for FPGAs (Abstract Only). FPGA 2016: 276 - [c44]Kumar H. B. Chethan, Nachiket Kapre:
Hoplite-DSP: Harnessing the Xilinx DSP48 multiplexers to efficiently support NoCs on FPGAs. FPL 2016: 1-10 - [c43]Nachiket Kapre, Samuel Bayliss:
Survey of domain-specific languages for FPGA computing. FPL 2016: 1-12 - [c42]Sidharth Maheshwari, Gourav Modi, Siddhartha, Nachiket Kapre:
Vector FPGA acceleration of 1-D DWT computations using sparse matrix skeletons. FPL 2016: 1-4 - [c41]Que Yanghua, Harnhua Ng, Nachiket Kapre:
Boosting convergence of timing closure using feature selection in a Learning-driven approach. FPL 2016: 1-9 - [c40]Kumar H. B. Chethan, Shubham Agarwal, Nachiket Kapre:
Deflection routing for multi-level FPGA overlay NoCs. FPT 2016: 149-156 - [c39]Deheng Ye, Zhenchang Xing, Chee Yong Foo, Jing Li, Nachiket Kapre:
Learning to Extract API Mentions from Informal Natural Language Discussions. ICSME 2016: 389-399 - [c38]Deheng Ye, Zhenchang Xing, Jing Li, Nachiket Kapre:
Software-specific part-of-speech tagging: an experimental study on stack overflow. SAC 2016: 1378-1385 - [c37]Deheng Ye, Zhenchang Xing, Chee Yong Foo, Zi Qun Ang, Jing Li, Nachiket Kapre:
Software-Specific Named Entity Recognition in Software Engineering Social Content. SANER 2016: 90-101 - 2015
- [j6]Nachiket Kapre, Pradeep Moorthy:
A Case for Embedded FPGA-based SoCs in Energy-Efficient Acceleration of Graph Problems. Supercomput. Front. Innov. 2(3): 76-86 (2015) - [j5]Abid Rafique, George A. Constantinides, Nachiket Kapre:
Communication Optimization of Iterative Sparse Matrix-Vector Multiply on GPUs and FPGAs. IEEE Trans. Parallel Distributed Syst. 26(1): 24-34 (2015) - [c36]Nachiket Kapre:
Custom FPGA-based soft-processors for sparse graph acceleration. ASAP 2015: 9-16 - [c35]Nachiket Kapre:
Sparse Graph Processing with Soft-Processors. FCCM 2015: 33 - [c34]Pradeep Moorthy, Nachiket Kapre:
Zedwulf: Power-Performance Tradeoffs of a 32-Node Zynq SoC Cluster. FCCM 2015: 68-75 - [c33]Gopalakrishna Hegde, Nachiket Kapre:
Energy-Efficient Acceleration of OpenCV Saliency Computation Using Soft Vector Processors. FCCM 2015: 76-83 - [c32]Nachiket Kapre, Bibin Chandrashekaran, Harnhua Ng, Kirvy Teo:
Driving Timing Convergence of FPGA Designs through Machine Learning and Cloud Computing. FCCM 2015: 119-126 - [c31]Nachiket Kapre, Harnhua Ng, Kirvy Teo, Jaco Naude:
InTime: A Machine Learning Approach for Efficient Selection of FPGA CAD Tool Parameters. FPGA 2015: 23-26 - [c30]Hui Yan Cheah, Suhaib A. Fahmy, Nachiket Kapre:
On Data Forwarding in Deeply Pipelined Soft Processors. FPGA 2015: 181-189 - [c29]Siddhartha, Nachiket Kapre:
FPGA Acceleration of Irregular Iterative Computations using Criticality-Aware Dataflow Optimizations (Abstract Only). FPGA 2015: 277 - [c28]Nachiket Kapre, Jan Gray:
Hoplite: Building austere overlay NoCs for FPGAs. FPL 2015: 1-8 - [c27]Nachiket Kapre, Jayakrishnan Selva Kumar, Parjanya Gupta, Sagar Shrishailappa Masuti, Sylvain Barbot:
Limits of FPGA acceleration of 3D Green's Function computation for geophysical applications. FPL 2015: 1-8 - [c26]Nachiket Kapre, Han Jianglei, Andrew Bean, Pradeep Moorthy, Siddhartha:
GraphMMU: Memory Management Unit for Sparse Graph Accelerators. IPDPS Workshops 2015: 113-120 - [c25]Lim Hui Hui, Nachiket Kapre:
Enhancing Speedups for FPGA Accelerated SPICE through Frequency Scaling and Precision Reduction. IPDPS Workshops 2015: 163-169 - [c24]Andrew Bean, Nachiket Kapre, Peter Y. K. Cheung:
G-DMA: improving memory access performance for hardware accelerated sparse graph computation. ReConFig 2015: 1-6 - 2014
- [c23]Siddhartha, Nachiket Kapre:
Breaking Sequential Dependencies in FPGA-Based Sparse LU Factorization. FCCM 2014: 60-63 - [c22]Edward A. Stott, Joshua M. Levine, Peter Y. K. Cheung, Nachiket Kapre:
Timing Fault Detection in FPGA-Based Circuits. FCCM 2014: 96-99 - [c21]Deheng Ye, Nachiket Kapre:
MixFX-SCORE: Heterogeneous Fixed-Point Compilation of Dataflow Computations. FCCM 2014: 206-209 - [c20]Soh Jun Jie, Nachiket Kapre:
Comparing soft and hard vector processing in FPGA-based embedded systems. FPL 2014: 1-7 - [c19]Siddhartha, Nachiket Kapre:
Heterogeneous dataflow architectures for FPGA-based sparse LU factorization. FPL 2014: 1-4 - [c18]Hui Yan Cheah, Suhaib A. Fahmy, Nachiket Kapre:
Analysis and optimization of a deeply pipelined FPGA soft processor. FPT 2014: 235-238 - [c17]Siddhartha, Nachiket Kapre:
Fanout decomposition dataflow optimizations for FPGA-based Sparse LU factorization. FPT 2014: 252-255 - [c16]Sagar Shrishailappa Masuti, Sylvain Barbot, Nachiket Kapre:
Relax-Miracle: GPU parallelization of semi-analytic fourier-domain solvers for earthquake modeling. HiPC 2014: 1-10 - 2013
- [c15]Abid Rafique, Nachiket Kapre, George A. Constantinides:
Application Composition and Communication Optimization in Iterative Solvers Using FPGAs. FCCM 2013: 153-160 - [c14]Nachiket Kapre:
Exploiting Input Parameter Uncertainty for Reducing Datapath Precision of SPICE Device Models. FCCM 2013: 189-197 - [c13]Kizheppatt Vipin, Shanker Shreejith, Dulitha Gunasekera, Suhaib A. Fahmy, Nachiket Kapre:
System-level FPGA device driver with high-level synthesis support. FPT 2013: 128-135 - 2012
- [j4]Nachiket Kapre, André DeHon:
${\rm SPICE}^2$: Spatial Processors Interconnected for Concurrent Execution for Accelerating the SPICE Circuit Simulator Using an FPGA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(1): 9-22 (2012) - [c12]Abid Rafique, Nachiket Kapre, George A. Constantinides:
A High Throughput FPGA-Based Implementation of the Lanczos Method for the Symmetric Extremal Eigenvalue Problem. ARC 2012: 239-250 - [c11]Hélène Martorell, Nachiket Kapre:
FX-SCORE: A Framework for Fixed-Point Compilation of SPICE Device Models Using Gappa++. FCCM 2012: 77-84 - [c10]Abid Rafique, Nachiket Kapre, George A. Constantinides:
Enhancing performance of Tall-Skinny QR factorization using FPGAs. FPL 2012: 443-450 - 2011
- [b1]Nachiket Kapre:
SPICE²: A Spatial, Parallel Architecture for Accelerating the Spice Circuit Simulator. California Institute of Technology, USA, 2011 - [j3]Nachiket Kapre, André DeHon:
An NoC Traffic Compiler for Efficient FPGA Implementation of Sparse Graph-Oriented Workloads. Int. J. Reconfigurable Comput. 2011: 745147:1-745147:14 (2011) - [j2]Michael DeLorimier, Nachiket Kapre, Nikil Mehta, André DeHon:
Spatial hardware implementation for sparse graph algorithms in GraphStep. ACM Trans. Auton. Adapt. Syst. 6(3): 17:1-17:20 (2011) - [c9]Nachiket Kapre, André DeHon:
VLIW-SCORE: Beyond C for sequential control of SPICE FPGA acceleration. FPT 2011: 1-9 - 2010
- [c8]Nachiket Kapre, André DeHon:
An NoC Traffic Compiler for efficient FPGA implementation of Parallel Graph Applications. ReCoSoC 2010: 87-94
2000 – 2009
- 2009
- [j1]Karl Papadantonakis, Nachiket Kapre, Stephanie Chan, André DeHon:
Pipelining Saturated Accumulation. IEEE Trans. Computers 58(2): 208-219 (2009) - [c7]Nachiket Kapre, André DeHon:
Accelerating SPICE Model-Evaluation using FPGAs. FCCM 2009: 37-44 - [c6]Nachiket Kapre, André DeHon:
Performance comparison of single-precision SPICE Model-Evaluation on FPGA, GPU, Cell, and multi-core processors. FPL 2009: 65-72 - 2007
- [c5]Nachiket Kapre, André DeHon:
Optimistic Parallelization of Floating-Point Accumulation. IEEE Symposium on Computer Arithmetic 2007: 205-216 - 2006
- [c4]Michael DeLorimier, Nachiket Kapre, Nikil Mehta, Dominic Rizzo, Ian Eslick, Raphael Rubin, Tomás E. Uribe, Thomas F. Knight Jr., André DeHon:
GraphStep: A System Architecture for Sparse-Graph Algorithms. FCCM 2006: 143-151 - [c3]Nachiket Kapre, Nikil Mehta, Michael DeLorimier, Raphael Rubin, Henry Barnor, Michael J. Wilson, Michael G. Wrighton, André DeHon:
Packet Switched vs. Time Multiplexed FPGA Overlay Networks. FCCM 2006: 205-216 - 2005
- [c2]Karl Papadantonakis, Nachiket Kapre, Stephanie Chan, André DeHon:
Pipelining Saturated Accumulation. FPT 2005: 19-26 - 2004
- [c1]André DeHon, Joshua Adams, Michael DeLorimier, Nachiket Kapre, Yuki Matsuda, Helia Naeimi, Michael C. Vanier, Michael G. Wrighton:
Design Patterns for Reconfigurable Computing. FCCM 2004: 13-23
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from 
to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-09-22 00:34 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
