"Vector FPGA acceleration of 1-D DWT computations using sparse matrix ..."

Sidharth Maheshwari et al. (2016)

> Home

Details and statistics

DOI: 10.1109/FPL.2016.7577361

access: closed

type: Conference or Workshop Paper

metadata version: 2017-10-19

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/fpl/MaheshwariMSK16
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/fpl/MaheshwariMSK16
Sidharth Maheshwari, Gourav Modi, Siddhartha, Nachiket Kapre:
Vector FPGA acceleration of 1-D DWT computations using sparse matrix skeletons. FPL 2016: 1-4

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.