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2020 – today
- 2024
[j7]Hechen Wang
, Peter Devine, James Tizard, Seyed Reza Shahamiri, Kelly Blincoe:
Conversation in forums: How software forum posts discuss potential development insights. J. Syst. Softw. 215: 112108 (2024)- [c13]Hechen Wang, Renzhi Liu, Richard Dorrance, Deepak Dasalukunte, Niranjan Gowda, Brent R. Carlton:
A PVT Robust 8-Bit Signed Analog Compute-In-Memory Accelerator with Integrated Activation Functions for AI Applications. VLSI Technology and Circuits 2024: 1-2 - 2023
- [j6]Hechen Wang, Renzhi Liu, Richard Dorrance, Deepak Dasalukunte, Dan Lake, Brent R. Carlton:
A Charge Domain SRAM Compute-in-Memory Macro With C-2C Ladder-Based 8-Bit MAC Unit in 22-nm FinFET Process for Edge Inference. IEEE J. Solid State Circuits 58(4): 1037-1050 (2023) - [j5]Richard Dorrance, Deepak Dasalukunte, Hechen Wang, Renzhi Liu, Brent R. Carlton:
An Energy-Efficient Bayesian Neural Network Accelerator With CiM and a Time-Interleaved Hadamard Digital GRNG Using 22-nm FinFET. IEEE J. Solid State Circuits 58(10): 2826-2838 (2023) - [j4]James Tizard, Peter Devine, Hechen Wang, Kelly Blincoe:
A Software Requirements Ecosystem: Linking Forum, Issue Tracker, and FAQs for Requirements Management. IEEE Trans. Software Eng. 49(4): 2381-2393 (2023) - 2022
- [c12]Peter Devine, James Tizard, Hechen Wang, Yun Sing Koh, Kelly Blincoe:
What's Inside a Cluster of Software User Feedback: A Study of Characterisation Methods. RE 2022: 189-200 - [c11]Hechen Wang, Renzhi Liu, Richard Dorrance, Deepak Dasalukunte, Xiaosen Liu, Dan Lake, Brent R. Carlton, May Wu:
A 32.2 TOPS/W SRAM Compute-in-Memory Macro Employing a Linear 8-bit C-2C Ladder for Charge Domain Computation in 22nm for Edge Inference. VLSI Technology and Circuits 2022: 36-37 - 2021
- [c10]Hechen Wang, Peter Devine, James Tizard, Seyed Reza Shahamiri, Kelly Blincoe:
The Use of Sub-forums in Software Product Forums. RE Workshops 2021: 293-297 - 2020
- [j3]Hechen Wang, Fa Foster Dai, Zhan Su, Yanjie Wang:
Sub-Sampling Direct RF-to-Digital Converter With 1024-APSK Modulation for High Throughput Polar Receiver. IEEE J. Solid State Circuits 55(4): 1064-1076 (2020) - [c9]Richard Dorrance, Andrey Belogolovy, Hechen Wang, Xue Zhang:
A Digital Root Based Modular Reduction Technique for Power Efficient, Fault Tolerance in FPGAs. FPL 2020: 341-346
2010 – 2019
- 2019
- [c8]Zhan Su, Hechen Wang, Haoyi Zhao, Zhenqi Chen, Yanjie Wang, Fa Foster Dai:
A 280MS/s 12b SAR-Assisted Hybrid ADC with Time Domain Sub-Range Quantizer in 45nm CMOS. CICC 2019: 1-4 - [c7]Zhan Su, Hechen Wang, Haoyi Zhao, Xiao Liu, Fa Foster Dai:
An 8-bit 80-MS/s Fully Self-Timed SAR ADC with 3/2 Interleaved Comparators and High-Order PVT Stabilized HBT Bandgap Reference. ISCAS 2019: 1-4 - [c6]James Tizard, Hechen Wang, Lydia Yohannes, Kelly Blincoe:
Can a Conversation Paint a Picture? Mining Requirements In Software Forums. RE 2019: 17-27 - [c5]Hechen Wang, Zhan Su, Haoyi Zhao, Yanjie Wang, Fa Foster Dai:
A 3.8 mW Sub-Sampling Direct RF-to-Digital Converter for Polar Receiver Achieving 1.94 Gb/s Data Rate with 1024-APSK Modulation. VLSI Circuits 2019: 82- - 2018
- [j2]Hechen Wang, Fa Foster Dai, Hua Wang:
A Reconfigurable Vernier Time-to-Digital Converter With 2-D Spiral Comparator Array and Second-Order ΔΣ Linearization. IEEE J. Solid State Circuits 53(3): 738-749 (2018) - [c4]Taiyun Chi, Hechen Wang, Min-Yu Huang, Fa Foster Dai, Hua Wang:
A bidirectional lens-free digital-bits-in/-out 0.57mm2 terahertz nano-radio in CMOS with 49.3mW Peak power consumption supporting 50cm Internet-of-Things communication. CICC 2018: 1-4 - 2017
- [j1]Dongyi Liao, Hechen Wang, Fa Foster Dai, Yang Xu, Roc Berenguer, Sara Munoz Hermoso:
An 802.11a/b/g/n Digital Fractional-N PLL With Automatic TDC Linearity Calibration for Spur Cancellation. IEEE J. Solid State Circuits 52(5): 1210-1220 (2017) - [c3]Taiyun Chi, Hechen Wang, Min-Yu Huang, Fa Foster Dai, Hua Wang:
A bidirectional lens-free digital-bits-in/-out 0.57mm2 Terahertz nano-radio in CMOS with 49.3mW peak power consumption supporting 50cm Internet-of-Things communication. CICC 2017: 1-4 - [c2]Hechen Wang, Fa Foster Dai, Hua Wang:
A 330μW 1.25ps 400fs-INL vernier time-to-digital converter with 2D reconfigurable spiral arbiter array and 2nd-order ΔΣ linearization. CICC 2017: 1-4 - [c1]Hechen Wang, Fa Foster Dai:
A 14-Bit, 1-ps resolution, two-step ring and 2D Vernier TDC in 130nm CMOS technology. ESSCIRC 2017: 143-146
Coauthor Index
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