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Tao-Chun Yu
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2020 – today
- 2021
- [j4]Tao-Chun Yu, Shao-Yun Fang, Hsien-Shih Chiu, Kai-Shun Hu, Philip Hui-Yuh Tai, Cindy Chin-Fang Shen, Henry Sheng:
Pin Accessibility Prediction and Optimization With Deep-Learning-Based Pin Pattern Recognition. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(11): 2345-2356 (2021) - [c9]Tao-Chun Yu, Shao-Yun Fang, Hsien-Shih Chiu, Kai-Shun Hu, Chin-Hsiung Hsu, Philip Hui-Yuh Tai, Cindy Chin-Fang Shen:
Machine Learning-based Structural Pre-route Insertability Prediction and Improvement with Guided Backpropagation. ASP-DAC 2021: 678-683 - [c8]Kai-Shun Hu, Tao-Chun Yu, Ming-Jen Yang, Cindy Chin-Fang Shen:
2021 ICCAD CAD Contest Problem B: Routing with Cell Movement Advanced: Invited Paper. ICCAD 2021: 1-5 - 2020
- [j3]Yi-Hao Cheng, Tao-Chun Yu, Shao-Yun Fang:
Obstacle-Avoiding Length-Matching Bus Routing Considering Nonuniform Track Resources. IEEE Trans. Very Large Scale Integr. Syst. 28(8): 1881-1892 (2020) - [c7]Kai-Shun Hu, Ming-Jen Yang, Tao-Chun Yu, Guan-Chuen Chen:
ICCAD-2020 CAD contest in Routing with Cell Movement : Invited Talk. ICCAD 2020: 69:1-69:4 - [c6]Kai-Chuan Yang, Tao-Chun Yu, Shao-Yun Fang, Teng-Yuan Cheng, Yang-Chun Liu, Cindy Chin-Fang Shen:
Meshed Stack Via Design Considering Complicated Design Rules with Automatic Constraint Generation. ICCAD 2020: 149:1-149:8 - [c5]Yong Zhong, Tao-Chun Yu, Kai-Chuan Yang, Shao-Yun Fang:
Via Pillar-aware Detailed Placement. ISPD 2020: 17-24 - [c4]Tao-Chun Yu, Shao-Yun Fang, Hsien-Shih Chiu, Kai-Shun Hu, Philip Hui-Yuh Tai, Cindy Chin-Fang Shen, Henry Sheng:
Lookahead Placement Optimization with Cell Library-based Pin Accessibility Prediction via Active Learning. ISPD 2020: 65-72
2010 – 2019
- 2019
- [j2]Tao-Chun Yu, An-Jie Shih, Shao-Yun Fang:
Flip-Chip Routing With I/O Planning Considering Practical Pad Assignment Constraints. IEEE Trans. Very Large Scale Integr. Syst. 27(8): 1921-1932 (2019) - [c3]Tao-Chun Yu, Shao-Yun Fang, Hsien-Shih Chiu, Kai-Shun Hu, Philip Hui-Yuh Tai, Cindy Chin-Fang Shen, Henry Sheng:
Pin Accessibility Prediction and Optimization with Deep Learning-based Pin Pattern Recognition. DAC 2019: 220 - [c2]Yu-Hung Huang, Zhiyao Xie, Guan-Qi Fang, Tao-Chun Yu, Haoxing Ren, Shao-Yun Fang, Yiran Chen, Jiang Hu:
Routability-Driven Macro Placement with Embedded CNN-Based Prediction Model. DATE 2019: 180-185 - 2018
- [j1]Tao-Chun Yu, Shao-Yun Fang, Chia-Ching Chen, Yulong Sun, Poki Chen:
Device Array Layout Synthesis With Nonlinear Gradient Compensation for a High-Accuracy Current-Steering DAC. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(4): 717-728 (2018) - [c1]Tao-Chun Yu, Shao-Yun Fang:
Flip-chip routing with IO planning considering practical pad assignment constraints. ASP-DAC 2018: 521-526
Coauthor Index
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