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2020 – today
- 2024
[j8]Qiaochu Zhang
, Hsiang-Chun Cheng, Shiyu Su, Mike Shuo-Wei Chen:
Fractional-N Digital MDLL With Injection-Error Scrambling and Calibration. IEEE J. Solid State Circuits 59(1): 40-51 (2024)- [c21]Qiaochu Zhang, Shiyu Su, Baishakhi Rani Biswas, Sandeep Gupta, Mike Shuo-Wei Chen:
Synthesizable 10-bit Stochastic TDC Using Common-Mode Time Dithering and Passive Approximate Adder with 0.012mm2 Active Area in 12nm FinFET. VLSI Technology and Circuits 2024: 1-2 - [c20]Qiaochu Zhang, Shiyu Su, Zerui Liu, Hsiang-Chun Cheng, Zhengyi Qiu, Mayank Palaria, Jiacheng Ye, Deming Meng, Buyun Chen, Sushmit Hossain, Wei Wu, Mike Shuo-Wei Chen:
A Stochastic Analog SAT Solver in 65nm CMOS Achieving 6.6μs Average Solution Time with 100% Solvability for Hard 3-SAT Problems. VLSI Technology and Circuits 2024: 1-2 - 2023
- [j7]Ce Yang, Shiyu Su, Mike Shuo-Wei Chen:
Millimeter-Wave Receiver With Non-Uniform Time-Approximation Filter. IEEE J. Solid State Circuits 58(5): 1201-1211 (2023) - [c19]Hsiang-Chun Cheng, Shiyu Su, Mayank Palaria, Qiaochu Zhang, Ce Yang, Sushmit Hossain, Ryan M. Bena, Buyun Chen, Zerui Liu, Juzheng Liu, Rezwan A. Rasul, Quan Nguyen, Wei Wu, Mike Shuo-Wei Chen:
A Memristor-Based Analog Accelerator for Solving Quadratic Programming Problems. CICC 2023: 1-2 - [c18]Shiyu Su, Qiaochu Zhang, Mike Shuo-Wei Chen:
A 2GS/s 8.5-Bit Time-Based ADC using a Segmented Stochastic Flash TDC. CICC 2023: 1-2 - [c17]Mayank Palaria, Shiyu Su, Hsiang-Chun Cheng, Rezwan A. Rasul, Qiaochu Zhang, Soumya Mahapatra, Chong-Fatt Law, Sushmit Hossain, Ryan M. Bena, Wei Wu, Quan Nguyen, Mike Shuo-Wei Chen:
Analog Kalman Filter with Integration and Digitization via a Shared Thyristor-Based VCO for Sensor Fusion in 65 nm CMOS. ESSCIRC 2023: 213-216 - [c16]Qiaochu Zhang, Hsiang-Chun Cheng, Shiyu Su, Mike Shuo-Wei Chen:
A Fractional-N Digital MDLL with Injection-Error Scrambling and Background Third-Order DTC Delay Equalizer Achieving -67dBc Fractional Spur. ISSCC 2023: 226-227 - 2022
- [j6]Qiaochu Zhang, Shiyu Su, Cheng-Ru Ho, Mike Shuo-Wei Chen:
A Fractional-N Digital MDLL With Background Two-Point DTC Calibration. IEEE J. Solid State Circuits 57(1): 80-89 (2022) - [j5]Shiyu Su, Mike Shuo-Wei Chen:
SAW-Less Direct RF Transmitter With Multimode Noise Shaping and Tri-Level Time-Approximation Filter. IEEE J. Solid State Circuits 57(3): 906-916 (2022) - [c15]Shiyu Su, Qiaochu Zhang, Mohsen Hassanpourghadi, Juzheng Liu, Rezwan A. Rasul, Mike Shuo-Wei Chen:
Analog/Mixed-Signal Circuit Synthesis Enabled by the Advancements of Circuit Architectures and Machine Learning Algorithms. ASP-DAC 2022: 100-107 - [c14]Shiyu Su, Qiaochu Zhang, Juzheng Liu, Mohsen Hassanpourghadi, Rezwan A. Rasul, Mike Shuo-Wei Chen:
TAFA: Design Automation of Analog Mixed-Signal FIR Filters Using Time Approximation Architecture. ASP-DAC 2022: 526-531 - [c13]Shiyu Su, Mike Shuo-Wei Chen:
High-Speed Digital-to-Analog Converter Design Towards High Dynamic Range. CICC 2022: 1-8 - [c12]Qiaochu Zhang, Shiyu Su, Mike Shuo-Wei Chen:
A cost-efficient fully synthesizable stochastic time-to-digital converter design based on integral nonlinearity scrambling. DAC 2022: 1021-1026 - 2021
- [j4]Shiyu Su, Mike Shuo-Wei Chen:
A Time-Approximation Filter for Direct RF Transmitter. IEEE J. Solid State Circuits 56(7): 2018-2028 (2021) - [c11]Mohsen Hassanpourghadi, Shiyu Su, Rezwan A. Rasul, Juzheng Liu, Qiaochu Zhang, Mike Shuo-Wei Chen:
Circuit Connectivity Inspired Neural Network for Analog Mixed-Signal Functional Modeling. DAC 2021: 505-510 - [c10]Juzheng Liu, Shiyu Su, Meghna Madhusudan, Mohsen Hassanpourghadi, Samuel Saunders, Qiaochu Zhang, Rezwan A. Rasul, Yaguang Li, Jiang Hu, Arvind Kumar Sharma, Sachin S. Sapatnekar, Ramesh Harjani, Anthony Levi, Sandeep Gupta, Mike Shuo-Wei Chen:
From Specification to Silicon: Towards Analog/Mixed-Signal Design Automation using Surrogate NN Models with Transfer Learning. ICCAD 2021: 1-9 - [c9]Qiaochu Zhang, Shiyu Su, Cheng-Ru Ho, Mike Shuo-Wei Chen:
29.4 A Fractional-N Digital MDLL with Background Two-Point DTC Calibration Achieving -60dBc Fractional Spur. ISSCC 2021: 410-412 - [i2]Shiyu Su, Qiaochu Zhang, Mohsen Hassanpourghadi, Juzheng Liu, Rezwan A. Rasul, Mike Shuo-Wei Chen:
Analog/Mixed-Signal Circuit Synthesis Enabled by the Advancements of Circuit Architectures and Machine Learning Algorithms. CoRR abs/2112.07824 (2021) - [i1]Shiyu Su, Qiaochu Zhang, Juzheng Liu, Mohsen Hassanpourghadi, Rezwan A. Rasul, Mike Shuo-Wei Chen:
TAFA: Design Automation of Analog Mixed-Signal FIR Filters Using Time Approximation Architecture. CoRR abs/2112.07825 (2021) - 2020
- [c8]Qiaochu Zhang, Shiyu Su, Juzheng Liu, Mike Shuo-Wei Chen:
CEPA: CNN-based Early Performance Assertion Scheme for Analog and Mixed-Signal Circuit Simulation. ICCAD 2020: 118:1-118:9 - [c7]Juzheng Liu, Mohsen Hassanpourghadi, Qiaochu Zhang, Shiyu Su, Mike Shuo-Wei Chen:
Transfer Learning with Bayesian Optimization-Aided Sampling for Efficient AMS Circuit Modeling. ICCAD 2020: 119:1-119:9 - [c6]Shiyu Su:
Millimeter-Wave Communications with Beamforming for UAV-Assisted Railway Monitoring System. IoTaaS 2020: 721-731 - [c5]Shiyu Su, Mike Shuo-Wei Chen:
10.2 A SAW-Less Direct-Digital RF Modulator with Tri-Level Time-Approximation Filter and Reconfigurable Dual-Band Delta-Sigma Modulation. ISSCC 2020: 174-176
2010 – 2019
- 2019
- [c4]Shiyu Su, Mike Shuo-Wei Chen:
A 1-5GHz Direct-Digital RF Modulator with an Embedded Time-Approximation Filter Achieving -43dB EVM at 1024 QAM. VLSI Circuits 2019: 20- - 2018
- [j3]Shiyu Su, Mike Shuo-Wei Chen:
A 16-bit 12-GS/s Single-/Dual-Rate DAC With a Successive Bandpass Delta-Sigma Modulator Achieving <-67-dBc IM3 Within DC to 6-GHz Tunable Passbands. IEEE J. Solid State Circuits 53(12): 3517-3527 (2018) - [c3]Shiyu Su, Mike Shuo-Wei Chen:
A 16b 12GS/S single/dual-rate DAC with successive bandpass delta-sigma modulator achieving <-67dBc IM3 within DC-to-6GHz tunable passbands. ISSCC 2018: 362-364 - 2016
- [j2]Shiyu Su, Mike Shuo-Wei Chen:
A 12-Bit 2 GS/s Dual-Rate Hybrid DAC With Pulse-Error Pre-Distortion and In-Band Noise Cancellation Achieving > 74 dBc SFDR and <-80 dBc IM3 up to 1 GHz in 65 nm CMOS. IEEE J. Solid State Circuits 51(12): 2963-2978 (2016) - [c2]Shiyu Su, Mike Shuo-Wei Chen:
27.1 A 12b 2GS/s dual-rate hybrid DAC with pulsed timing-error pre-distortion and in-band noise Cancellation Achieving >74dBc SFDR up to 1GHz in 65nm CMOS. ISSCC 2016: 456-457 - 2015
- [j1]Shiyu Su, Tu-I Tsai, Praveen Kumar Sharma, Mike Shuo-Wei Chen:
A 12 bit 1 GS/s Dual-Rate Hybrid DAC With an 8 GS/s Unrolled Pipeline Delta-Sigma Modulator Achieving > 75 dB SFDR Over the Nyquist Band. IEEE J. Solid State Circuits 50(4): 896-907 (2015) - 2014
- [c1]Shiyu Su, Tu-I Tsai, Praveen Kumar Sharma, Mike Shuo-Wei Chen:
A 12-bit hybrid DAC with 8GS/s unrolled pipeline delta-sigma modulator achieving >75dB SFDR over 500MHz in 65nm CMOS. VLSIC 2014: 1-2
Coauthor Index
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