"A Stochastic Analog SAT Solver in 65nm CMOS Achieving 6.6μs Average ..."

Qiaochu Zhang et al. (2024)

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DOI: 10.1109/VLSITECHNOLOGYANDCIR46783.2024.10631503

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type: Conference or Workshop Paper

metadata version: 2025-03-03

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Qiaochu Zhang, Shiyu Su, Zerui Liu, Hsiang-Chun Cheng, Zhengyi Qiu, Mayank Palaria, Jiacheng Ye, Deming Meng, Buyun Chen, Sushmit Hossain, Wei Wu, Mike Shuo-Wei Chen:
A Stochastic Analog SAT Solver in 65nm CMOS Achieving 6.6μs Average Solution Time with 100% Solvability for Hard 3-SAT Problems. VLSI Technology and Circuits 2024: 1-2

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