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ORCIDJun Lin 0001
Person information
- affiliation: Nanjing University, School of Electronic Science and Engineering, Nanjing, China
- affiliation (PhD 2015): Lehigh University, Bethlehem, PA, USA
Other persons with the same name
- Jun Lin — disambiguation page
- Jun Lin 0002
![[0000-0002-2635-1816]](https://dblp.uni-trier.de./img/orcid-mark.12x12.png "0000-0002-2635-1816")
— Xi'an Jiaotong University, School of Management, China - Jun Lin 0003 — Jilin University, College of Instrumentation and Electrical Engineering, Changchun, China (and 1 more)
- Jun Lin 0004 — University of Sydney, School of Electrical and Information Engineering, NSW, Australia (and 1 more)
- Jun Lin 0005 — CRRC Zhuzhou Electric Company Ltd., Zhuzhou, China (and 2 more)
- Jun Lin 0006 — Shandong University, Joint SDU-NTU Centre for Artificial Intelligence Research (C-FAIR), China (and 1 more)
- Jun Lin 0007 — China Electronic Product Reliability and Environment Testing Research Institute, Guangzhou, China
- Jun Lin 0008 — China Center for Resource Satellite Data and Applications (CRESDA), Beijing, China (and 1 more)
- Jun Lin 0009 — Indiana University-Purdue University Indianapolis (IUPUI), School of Engineering and Technology, Indianapolis, IN, USA
- Jun Lin 0010 — Fuzhou First Hospital, Department of Gynecology and Obstetrics, Fuzhou, China
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2020 – today
- 2025
[j66]Chuanning Wang, Chao Fang, Xiao Wu, Zhongfeng Wang, Jun Lin:
SPEED: A Scalable RISC-V Vector Processor Enabling Efficient Multiprecision DNN Inference. IEEE Trans. Very Large Scale Integr. Syst. 33(1): 207-220 (2025)- 2024
- [j65]Jinming Lu, Hui Wang, Jun Lin, Zhongfeng Wang:
WinTA: An Efficient Reconfigurable CNN Training Accelerator With Decomposition Winograd. IEEE Trans. Circuits Syst. I Regul. Pap. 71(2): 634-645 (2024) - [j64]Yubo Shi, Meiqi Wang, Tianyu Cao, Jun Lin, Zhongfeng Wang:
TECO: A Unified Feature Map Compression Framework Based on Transform and Entropy. IEEE Trans. Neural Networks Learn. Syst. 35(12): 17856-17866 (2024) - [j63]Xiao Wu, Miaoxin Wang, Jun Lin, Zhongfeng Wang:
Amoeba: An Efficient and Flexible FPGA-Based Accelerator for Arbitrary-Kernel CNNs. IEEE Trans. Very Large Scale Integr. Syst. 32(6): 1086-1099 (2024) - [c87]Longwei Huang, Chao Fang, Qiong Li, Jun Lin, Zhongfeng Wang:
A Precision-Scalable RISC-V DNN Processor with On-Device Learning Capability at the Extreme Edge. ASPDAC 2024: 927-932 - [c86]Chuanning Wang, Chao Fang, Xiao Wu, Zhongfeng Wang, Jun Lin:
A Scalable RISC-V Vector Processor Enabling Efficient Multi-Precision DNN Inference. ISCAS 2024: 1-5 - [c85]Miaoxin Wang, Xiao Wu, Jun Lin, Zhongfeng Wang:
An FPGA-Based Accelerator Enabling Efficient Support for CNNs with Arbitrary Kernel Sizes. ISCAS 2024: 1-5 - [i23]Chuanning Wang, Chao Fang, Xiao Wu, Zhongfeng Wang, Jun Lin:
A Scalable RISC-V Vector Processor Enabling Efficient Multi-Precision DNN Inference. CoRR abs/2401.16872 (2024) - [i22]Miaoxin Wang, Xiao Wu, Jun Lin, Zhongfeng Wang:
An FPGA-Based Accelerator Enabling Efficient Support for CNNs with Arbitrary Kernel Sizes. CoRR abs/2402.14307 (2024) - [i21]Chuanning Wang, Chao Fang, Xiao Wu, Zhongfeng Wang, Jun Lin:
SPEED: A Scalable RISC-V Vector Processor Enabling Efficient Multi-Precision DNN Inference. CoRR abs/2409.14017 (2024) - 2023
- [j62]Siyuan Lu, Chenchen Zhou, Keli Xie, Jun Lin, Zhongfeng Wang:
Fast and Accurate FSA System Using ELBERT: An Efficient and Lightweight BERT. IEEE Trans. Signal Process. 71: 3821-3834 (2023) - [j61]Yangyang Chen, Suwen Song, Zhongfeng Wang, Jun Lin:
An Efficient Massive MIMO Detector Based on Approximate Expectation Propagation. IEEE Trans. Very Large Scale Integr. Syst. 31(5): 696-700 (2023) - [c84]Hui Wang, Jinming Lu, Jun Lin, Zhongfeng Wang:
An FPGA-Based Reconfigurable CNN Training Accelerator Using Decomposable Winograd. ISVLSI 2023: 1-6 - [i20]Longwei Huang, Chao Fang, Qiong Li, Jun Lin, Zhongfeng Wang:
A Precision-Scalable RISC-V DNN Processor with On-Device Learning Capability at the Extreme Edge. CoRR abs/2309.08186 (2023) - 2022
- [j60]Hao Wang, Xiangyu Yang, Yuanming Shi, Jun Lin:
A Proximal Iteratively Reweighted Approach for Efficient Network Sparsification. IEEE Trans. Computers 71(1): 185-196 (2022) - [j59]Jing Tian, Piaoyang Wang, Zhe Liu, Jun Lin, Zhongfeng Wang, Johann Großschädl:
Efficient Software Implementation of the SIKE Protocol Using a New Data Representation. IEEE Trans. Computers 71(3): 670-683 (2022) - [j58]Meiqi Wang, Liulu He, Jun Lin, Zhongfeng Wang:
Rethinking Adaptive Computing: Building a Unified Model Complexity-Reduction Framework With Adversarial Robustness. IEEE Trans. Neural Networks Learn. Syst. 33(4): 1803-1810 (2022) - [c83]Mingyang Xu, Jinming Lu, Zhongfeng Wang, Jun Lin:
An Efficient CNN Training Accelerator Leveraging Transposable Block Sparsity. AICAS 2022: 230-233 - [c82]Xin Cheng, Meiqi Wang, Yu-Bo Shi, Jun Lin, Zhongfeng Wang:
Magical-Decomposition: Winning Both Adversarial Robustness and Efficiency on Hardware. ICMLC 2022: 61-66 - [c81]Ziqi Su, Wendong Mao, Zhongfeng Wang, Jun Lin, Wenqiang Wang, Haitao Sun:
Accelerate Three-Dimensional Generative Adversarial Networks Using Fast Algorithm. ISCAS 2022: 31-35 - [c80]Chao Fang, Shouliang Guo, Wei Wu, Jun Lin, Zhongfeng Wang, Ming Kai Hsu, Lingzhi Liu:
An Efficient Hardware Accelerator for Sparse Transformer Neural Networks. ISCAS 2022: 2670-2674 - [c79]Peixiang Yang, Wendong Mao, Zhongfeng Wang, Jun Lin:
A Reconfigurable Approach for Deconvolutional Network Acceleration with Fast Algorithm. ISCAS 2022: 2685-2689 - [c78]Zilun Wang, Wendong Mao, Peixiang Yang, Zhongfeng Wang, Jun Lin:
An Efficient FPGA Accelerator for Point Cloud. SOCC 2022: 1-6 - [c77]Ziyang Jiang, Siyuan Lu, Jun Lin, Zhongfeng Wang:
Forecasting Stock Indexes with Metabolic DWT and MWA-GM(1,1). WCSP 2022: 516-521 - [i19]Zilun Wang, Wendong Mao, Peixiang Yang, Zhongfeng Wang, Jun Lin:
An Efficient FPGA Accelerator for Point Cloud. CoRR abs/2210.07803 (2022) - [i18]Siyuan Lu, Chenchen Zhou, Keli Xie, Shiyi Liu, Jun Lin, Zhongfeng Wang:
Fast and Accurate FSA System Using ELBERT: An Efficient and Lightweight BERT. CoRR abs/2211.08842 (2022) - 2021
- [j57]Suwen Song, Jing Tian, Jun Lin, Zhongfeng Wang:
An Improved Reliability-Based Decoding Algorithm for NB-LDPC Codes. IEEE Commun. Lett. 25(4): 1153-1157 (2021) - [j56]Jinming Lu, Chao Fang, Mingyang Xu, Jun Lin, Zhongfeng Wang:
Evaluations on Deep Neural Networks Training Using Posit Number System. IEEE Trans. Computers 70(2): 174-187 (2021) - [j55]Hangxuan Cui, Fakhreddine Ghaffari, Khoa Le, David Declercq, Jun Lin, Zhongfeng Wang:
Design of High-Performance and Area-Efficient Decoder for 5G LDPC Codes. IEEE Trans. Circuits Syst. I Regul. Pap. 68(2): 879-891 (2021) - [j54]Shuang Liang, Siyuan Lu, Jun Lin, Zhongfeng Wang:
Low-Latency Hardware Accelerator for Improved Engle-Granger Cointegration in Pairs Trading. IEEE Trans. Circuits Syst. I Regul. Pap. 68(7): 2911-2924 (2021) - [j53]Xiaoru Xie, Jun Lin, Zhongfeng Wang, Jinghe Wei:
An Efficient and Flexible Accelerator Design for Sparse Convolutional Neural Networks. IEEE Trans. Circuits Syst. I Regul. Pap. 68(7): 2936-2949 (2021) - [j52]Jing Tian, Jun Lin, Zhongfeng Wang:
Fast Modular Multipliers for Supersingular Isogeny-Based Post-Quantum Cryptography. IEEE Trans. Very Large Scale Integr. Syst. 29(2): 359-371 (2021) - [c76]Keyue Deng, Hangxuan Cui, Jun Lin, Zhongfeng Wang:
Counter Random Gradient Descent Bit-Flipping Decoder for LDPC Codes. ISVLSI 2021: 55-60 - [c75]Luyi Li, Jun Lin, Zhongfeng Wang:
PipeBSW: A Two-Stage Pipeline Structure for Banded Smith-Waterman Algorithm on FPGA. ISVLSI 2021: 182-187 - [c74]Haikuo Shao, Jinming Lu, Jun Lin, Zhongfeng Wang:
An FPGA-Based Reconfigurable Accelerator for Low-Bit DNN Training. ISVLSI 2021: 254-259 - [c73]Shize Zhao, Liulu He, Xiaoru Xie, Jun Lin, Zhongfeng Wang:
Automatic Generation of Dynamic Inference Architecture for Deep Neural Networks. SiPS 2021: 117-122 - 2020
- [j51]Wenjie Li, Jun Lin, Zhongfeng Wang:
Multi-Layer Generalized Integrated Interleaved Codes. IEEE Commun. Lett. 24(9): 1880-1884 (2020) - [j50]Jiapeng Luo, Jiaying Liu, Jun Lin, Zhongfeng Wang:
A lightweight face detector by integrating the convolutional neural network with the image pyramid. Pattern Recognit. Lett. 133: 180-187 (2020) - [j49]Jing Tian, Suwen Song, Jun Lin, Zhongfeng Wang:
Optimized Trellis-Based Min-Max Decoder for NB-LDPC Codes. IEEE Trans. Circuits Syst. II Express Briefs 67-II(1): 57-61 (2020) - [j48]Yuxing Chen, Hangxuan Cui, Jun Lin, Zhongfeng Wang:
Fine-Grained Bit-Flipping Decoding for LDPC Codes. IEEE Trans. Circuits Syst. II Express Briefs 67-II(5): 896-900 (2020) - [j47]Suwen Song, Hangxuan Cui, Jing Tian, Jun Lin, Zhongfeng Wang:
A Novel Iterative Reliability-Based Majority-Logic Decoder for NB-LDPC Codes. IEEE Trans. Circuits Syst. II Express Briefs 67-II(8): 1399-1403 (2020) - [j46]Wenjian Liu, Jun Lin, Zhongfeng Wang:
A Precision-Scalable Energy-Efficient Convolutional Neural Network Accelerator. IEEE Trans. Circuits Syst. 67-I(10): 3484-3497 (2020) - [j45]Danyang Zhu, Siyuan Lu, Meiqi Wang, Jun Lin, Zhongfeng Wang:
Efficient Precision-Adjustable Architecture for Softmax Function in Deep Learning. IEEE Trans. Circuits Syst. 67-II(12): 3382-3386 (2020) - [j44]Wendong Mao, Jun Lin, Zhongfeng Wang:
F-DNA: Fast Convolution Architecture for Deconvolutional Network Acceleration. IEEE Trans. Very Large Scale Integr. Syst. 28(8): 1867-1880 (2020) - [j43]Hangxuan Cui, Jun Lin, Zhongfeng Wang:
Information Storage Bit-Flipping Decoder for LDPC Codes. IEEE Trans. Very Large Scale Integr. Syst. 28(11): 2464-2468 (2020) - [c72]Liulu He, Xiaoru Xie, Jun Lin, Zhongfeng Wang:
Efficient FPGA design for Convolutions in CNN based on FFT-pruning. APCCAS 2020: 27-30 - [c71]Chao Ni, Jinming Lu, Jun Lin, Zhongfeng Wang:
LBFP: Logarithmic Block Floating Point Arithmetic for Deep Neural Networks. APCCAS 2020: 201-204 - [c70]Yufei Ma, Yuan Du, Li Du, Jun Lin, Zhongfeng Wang:
In-Memory Computing: The Next-Generation AI Computing Paradigm. ACM Great Lakes Symposium on VLSI 2020: 265-270 - [c69]Binjing Li, Keli Xie, Siyuan Lu, Jun Lin, Zhongfeng Wang:
LSTM-Based Quantitative Trading Using Dynamic K-Top and Kelly Criterion. IJCNN 2020: 1-8 - [c68]Shuang Liang, Siyuan Lu, Jun Lin, Zhongfeng Wang:
Hardware Accelerator for Engle-Granger Cointegration in Pairs Trading. ISCAS 2020: 1-5 - [c67]Yujie Zhang, Jiajun Wu, Minghao Li, Jun Lin, Zhongfeng Wang:
A Three-Level Scoring System for Fast Similarity Evaluation Based on Smith-Waterman Algorithm. ISCAS 2020: 1-5 - [c66]Jing Zeng, Jun Lin, Zhongfeng Wang:
A Serial Maximum-likelihood Detection Algorithm for Massive MIMO Systems. NEWCAS 2020: 78-81 - [c65]Peixiang Yang, Wendong Mao, Jun Lin, Zhongfeng Wang:
A Computation-Efficient Solution for Acceleration of Generative Adversarial Network. NEWCAS 2020: 210-213 - [c64]Meiqi Wang, Ruixin Xue, Jun Lin, Zhongfeng Wang:
Exploring Quantization in Few-Shot Learning. NEWCAS 2020: 279-282 - [c63]Binjing Li, Fenggui Liu, Jun Lin, Zhongfeng Wang:
Financial Time Series Forecasting Model Based on EMD and Rolling Grey Model. SiPS 2020: 1-6 - [c62]Jinming Lu, Jun Lin, Zhongfeng Wang:
A Reconfigurable DNN Training Accelerator on FPGA. SiPS 2020: 1-6 - [c61]Haonan Wang, Yuchen Mei, Jun Lin, Zhongfeng Wang:
Temporal Residual Feature Learning for Efficient 3D Convolutional Neural Network on Action Recognition Task. SiPS 2020: 1-6 - [c60]Siyuan Lu, Meiqi Wang, Shuang Liang, Jun Lin, Zhongfeng Wang:
Hardware Accelerator for Multi-Head Attention and Position-Wise Feed-Forward in the Transformer. SoCC 2020: 84-89 - [c59]Shouliang Guo, Chao Fang, Jun Lin, Zhongfeng Wang:
A Configurable FPGA Accelerator of Bi-LSTM Inference with Structured Sparsity. SoCC 2020: 174-179 - [i17]Siyuan Lu, Meiqi Wang, Shuang Liang, Jun Lin, Zhongfeng Wang:
Hardware Accelerator for Multi-Head Attention and Position-Wise Feed-Forward in the Transformer. CoRR abs/2009.08605 (2020) - [i16]Jing Tian, Jun Lin, Zhongfeng Wang:
Ultra-Fast Modular Multiplication Implementation for Isogeny-Based Post-Quantum Cryptography. IACR Cryptol. ePrint Arch. 2020: 246 (2020) - [i15]Jing Tian, Piaoyang Wang, Zhe Liu, Jun Lin, Zhongfeng Wang, Johann Großschädl:
Faster Software Implementation of the SIKE Protocol Based on A New Data Representation. IACR Cryptol. ePrint Arch. 2020: 660 (2020)
2010 – 2019
- 2019
- [j42]Jing Tian, Suwen Song, Jun Lin, Zhongfeng Wang:
Efficient T-EMS Based Decoding Algorithms for High-Order LDPC Codes. IEEE Access 7: 50980-50992 (2019) - [j41]Siyuan Lu, Jinming Lu, Jun Lin, Zhongfeng Wang:
A Hardware-Oriented and Memory-Efficient Method for CTC Decoding. IEEE Access 7: 120681-120694 (2019) - [j40]Meiqi Wang, Zhisheng Wang, Jinming Lu, Jun Lin, Zhongfeng Wang:
E-LSTM: An Efficient Hardware Architecture for Long Short-Term Memory. IEEE J. Emerg. Sel. Topics Circuits Syst. 9(2): 280-291 (2019) - [j39]Wenjie Li, Jing Tian, Jun Lin, Zhongfeng Wang:
Modified GII-BCH Codes for Low-Complexity and Low-Latency Encoders. IEEE Commun. Lett. 23(5): 785-788 (2019) - [j38]Yangcan Zhou, Jun Lin, Zhongfeng Wang:
Improved Fast-SSC-Flip Decoding of Polar Codes. IEEE Commun. Lett. 23(6): 950-953 (2019) - [j37]Yizhi Wang, Jun Lin, Zhongfeng Wang:
FPAP: A Folded Architecture for Energy-Quality Scalable Convolutional Neural Networks. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(1): 288-301 (2019) - [j36]Yangcan Zhou, Zhiyu Chen, Jun Lin, Zhongfeng Wang:
A High-Speed Successive-Cancellation Decoder for Polar Codes Using Approximate Computing. IEEE Trans. Circuits Syst. II Express Briefs 66-II(2): 227-231 (2019) - [j35]Congyi Zhu, Jun Lin, Zhongfeng Wang:
A New Clock Phase Calibration Method in High-Speed and High-Resolution DACs. IEEE Trans. Circuits Syst. II Express Briefs 66-II(2): 332-336 (2019) - [j34]Congyi Zhu, Jun Lin, Zhongfeng Wang:
Background Calibration of Comparator Offsets in SHA-Less Pipelined ADCs. IEEE Trans. Circuits Syst. II Express Briefs 66-II(2): 357-361 (2019) - [j33]Hangxuan Cui, Jun Lin, Zhongfeng Wang:
An Efficient Post-Processor for Lowering the Error Floor of LDPC Codes. IEEE Trans. Circuits Syst. II Express Briefs 66-II(2): 397-401 (2019) - [j32]Wenjie Li, Jun Lin, Zhongfeng Wang:
A 124-Gb/s Decoder for Generalized Integrated Interleaved Codes. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(8): 3174-3187 (2019) - [j31]Hangxuan Cui, Jun Lin, Zhongfeng Wang:
An Improved Gradient Descent Bit-Flipping Decoder for LDPC Codes. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(8): 3188-3200 (2019) - [j30]Congyi Zhu, Renrong Liang, Jun Lin, Zhongfeng Wang, Li Li:
Analysis and Design of a Large Dither Injection Circuit for Improving Linearity in Pipelined ADCs. IEEE Trans. Very Large Scale Integr. Syst. 27(9): 2008-2020 (2019) - [c58]Hangxuan Cui, Khoa LeTrung, Fakhreddine Ghaffari, David Declercq, Jun Lin, Zhongfeng Wang:
An Enhanced Offset Min-Sum decoder for 5G LDPC Codes. APCC 2019: 490-495 - [c57]Suwen Song, Jing Tian, Jun Lin, Zhongfeng Wang:
Redundancy-Aided Iterative Reliability-Based Majority-Logic Decoding for NB-LDPC Codes. ASICON 2019: 1-4 - [c56]Haonan Wang, Wenjian Liu, Tianyi Xu, Jun Lin, Zhongfeng Wang:
A Low-latency Sparse-Winograd Accelerator for Convolutional Neural Networks. ICASSP 2019: 1448-1452 - [c55]Yangcan Zhou, Jun Lin, Zhongfeng Wang:
A New Fast-SSC-Flip Decoding of Polar Codes. ICC 2019: 1-6 - [c54]Chunhua Deng, Fangxuan Sun, Xuehai Qian, Jun Lin, Zhongfeng Wang, Bo Yuan:
TIE: energy-efficient tensor train-based inference engine for deep neural network. ISCA 2019: 264-278 - [c53]Hangxuan Cui, Jun Lin, Suwen Song, Zhongfeng Wang:
A New Probabilistic Gradient Descent Bit Flipping Decoder for LDPC Codes. ISCAS 2019: 1-5 - [c52]Wenjian Liu, Jun Lin, Zhongfeng Wang:
USCA: A Unified Systolic Convolution Array Architecture for Accelerating Sparse Neural Network. ISCAS 2019: 1-5 - [c51]Wendong Mao, Jichen Wang, Jun Lin, Zhongfeng Wang:
Methodology for Efficient Reconfigurable Architecture of Generative Neural Network. ISCAS 2019: 1-5 - [c50]Suwen Song, Jing Tian, Jun Lin, Zhongfeng Wang:
A Novel Low-Complexity Joint Coding and Decoding Algorithm for NB-LDPC Codes. ISCAS 2019: 1-5 - [c49]Hangxuan Cui, Khoa Le, Fakhreddine Ghaffari, David Declercq, Jun Lin, Zhongfeng Wang:
A Decomposition Mapping based Quantized Belief Propagation Decoding for 5G LDPC Codes. ISCIT 2019: 616-620 - [c48]Xiaoru Xie, Fangxuan Sun, Jun Lin, Zhongfeng Wang:
Fast-ABC: A Fast Architecture for Bottleneck-Like Based Convolutional Neural Networks. ISVLSI 2019: 1-6 - [c47]Zengchao Yan, Jun Lin, Zhongfeng Wang:
A Low-Complexity RS Decoder for Triple-Error-Correcting RS Codes. ISVLSI 2019: 489-494 - [c46]Jing Zeng, Yangcan Zhou, Jun Lin, Zhongfeng Wang:
Hardware Implementation of Improved Fast-SSC-Flip Decoder for Polar Codes. ISVLSI 2019: 580-585 - [c45]Zengchao Yan, Wenjie Li, Jun Lin, Zhongfeng Wang:
A Low-Complexity Error-and-Erasure Decoding Algorithm for t=2 RS Codes. SiPS 2019: 43-47 - [c44]Wenjian Liu, Xiayuan Wen, Jun Lin, Zhongfeng Wang, Li Du:
EAGLE: Exploiting Essential Address in Both Weight and Activation to Accelerate CNN Computing. SiPS 2019: 73-78 - [c43]Jing Tian, Jun Lin, Zhongfeng Wang:
Ultra-Fast Modular Multiplication Implementation for Isogeny-Based Post-Quantum Cryptography. SiPS 2019: 97-102 - [c42]Meiqi Wang, Jianqiao Mo, Jun Lin, Zhongfeng Wang, Li Du:
DynExit: A Dynamic Early-Exit Strategy for Deep Residual Networks. SiPS 2019: 178-183 - [c41]Jing Zeng, Jun Lin, Zhongfeng Wang, Yun Chen:
Hybrid Preconditioned CG Detection with Sequential Update for Massive MIMO Systems. SiPS 2019: 207-212 - [c40]Siyuan Lu, Jinming Lu, Jun Lin, Zhongfeng Wang, Li Du:
A Low-Latency and Low-Complexity Hardware Architecture for CTC Beam Search Decoding. SiPS 2019: 352-357 - [c39]Jinming Lu, Siyuan Lu, Zhisheng Wang, Chao Fang, Jun Lin, Zhongfeng Wang, Li Du:
Training Deep Neural Networks Using Posit Number System. SoCC 2019: 62-67 - [i14]Siyuan Lu, Jinming Lu, Jun Lin, Zhongfeng Wang:
A Hardware-Oriented and Memory-Efficient Method for CTC Decoding. CoRR abs/1905.03175 (2019) - [i13]Haonan Wang, Jun Lin, Zhongfeng Wang:
Design Light-weight 3D Convolutional Networks for Video Recognition Temporal Residual, Fully Separable Block, and Fast Algorithm. CoRR abs/1905.13388 (2019) - [i12]Jinming Lu, Siyuan Lu, Zhisheng Wang, Chao Fang, Jun Lin, Zhongfeng Wang, Li Du:
Training Deep Neural Networks Using Posit Number System. CoRR abs/1909.03831 (2019) - [i11]Jing Tian, Zhe Liu, Jun Lin, Zhongfeng Wang, Binjing Li:
High-Speed Modular Multipliers for Isogeny-Based Post-Quantum Cryptography. IACR Cryptol. ePrint Arch. 2019: 1206 (2019) - 2018
- [j29]Qiong Wu, Fan Zhang, Hao Wang, Jun Lin, Yang Liu:
Parameter-Free ℓp-Box Decoding of LDPC Codes. IEEE Commun. Lett. 22(7): 1318-1321 (2018) - [j28]Zhisheng Wang, Jun Lin, Zhongfeng Wang:
Hardware-Oriented Compression of Long Short-Term Memory for Efficient Inference. IEEE Signal Process. Lett. 25(7): 984-988 (2018) - [j27]Jing Tian, Jun Lin, Zhongfeng Wang:
A 21.66 Gbps Nonbinary LDPC Decoder for High-Speed Communications. IEEE Trans. Circuits Syst. II Express Briefs 65-II(2): 226-230 (2018) - [j26]Jichen Wang, Jun Lin, Zhongfeng Wang:
Efficient Hardware Architectures for Deep Convolutional Neural Network. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(6): 1941-1953 (2018) - [j25]Jing Zeng, Jun Lin, Zhongfeng Wang:
An Improved Gauss-Seidel Algorithm and Its Efficient Architecture for Massive MIMO Systems. IEEE Trans. Circuits Syst. II Express Briefs 65-II(9): 1194-1198 (2018) - [j24]Yizhi Wang, Jun Lin, Zhongfeng Wang:
An Energy-Efficient Architecture for Binary Weight Convolutional Neural Networks. IEEE Trans. Very Large Scale Integr. Syst. 26(2): 280-293 (2018) - [j23]Jin Sha, Jingbo Liu, Jun Lin, Zhongfeng Wang:
A Stage-Combined Belief Propagation Decoder for Polar Codes. J. Signal Process. Syst. 90(5): 687-694 (2018) - [j22]Jing Zeng, Jun Lin, Zhongfeng Wang:
Low Complexity Message Passing Detection Algorithm for Large-Scale MIMO Systems. IEEE Wirel. Commun. Lett. 7(5): 708-711 (2018) - [c38]Haonan Wang, Jun Lin, Yi Xie, Bo Yuan, Zhongfeng Wang:
Efficient Reconfigurable Hardware Core for Convolutional Neural Networks. ACSSC 2018: 777-781 - [c37]Zengchao Yan, Wenjie Li, Jun Lin, Zhongfeng Wang:
Fast and Low-Complexity Decoding Algorithm and Architecture for Quadruple-Error-Correcting RS codes. APCCAS 2018: 191-194 - [c36]Meiqi Wang, Siyuan Lu, Danyang Zhu, Jun Lin, Zhongfeng Wang:
A High-Speed and Low-Complexity Architecture for Softmax Function in Deep Learning. APCCAS 2018: 223-226 - [c35]Jing Tian, Jun Lin, Zhongfeng Wang:
Analysis of the Dual-Threshold-Based Shrinking Scheme for Efficient NB-LDPC Decoding. APCCAS 2018: 227-230 - [c34]Xin Jin, Jun Lin, Zhongfeng Wang:
A Novel Compiler for Regular Expression Matching Engine Construction. APCCAS 2018: 251-256 - [c33]Fangxuan Sun, Jun Lin, Zhongfeng Wang:
Eadnet: Efficient Architecture for Decomposed Convolutional Neural Networks. ICASSP 2018: 1145-1149 - [c32]Menghui Xu, Shusen Jing, Jun Lin, Weikang Qian, Zaichen Zhang, Xiaohu You, Chuan Zhang:
Approximate Belief Propagation Decoder for Polar Codes. ICASSP 2018: 1169-1173 - [c31]Jing Tian, Jun Lin, Zhongfeng Wang:
An Efficient NB-LDPC Decoding Algorithm for Next-Generation Memories. ISCAS 2018: 1-5 - [c30]Yaqi Wang, Jun Lin, Zhongfeng Wang:
A New Soft-input Hard-output decoding algorithm for Turbo Product Codes. ISCAS 2018: 1-5 - [c29]Yizhi Wang, Jun Lin, Zhongfeng Wang:
An Efficient Convolution Core Architecture for Privacy-Preserving Deep Learning. ISCAS 2018: 1-5 - [c28]Yizhi Wang, Jun Lin, Zhongfeng Wang:
FPAP: A Folded Architecture for Efficient Computing of Convolutional Neural Networks. ISVLSI 2018: 503-508 - [c27]Fangxuan Sun, Jun Lin, Zhongfeng Wang:
An Optimized Architecture For Decomposed Convolutional Neural Networks. ISVLSI 2018: 516-521 - [c26]Jichen Wang, Jun Lin, Zhongfeng Wang:
Bandwidth Efficient Architectures for Convolutional Neural Network. SiPS 2018: 94-99 - [c25]Yangcan Zhou, Jun Lin, Jichen Wang, Zhongfeng Wang:
Approximate Comparator: Design and Analysis. SiPS 2018: 129-133 - [c24]Yahui Ji, Zhizhen Wu, Yifei Shen, Jun Lin, Zaichen Zhang, Xiaohu You, Chuan Zhang:
A Low-Complexity Massive MIMO Detection Algorithm Based on Matrix Partition. SiPS 2018: 158-163 - [i10]Zhisheng Wang, Fangxuan Sun, Jun Lin, Zhongfeng Wang, Bo Yuan:
SGAD: Soft-Guided Adaptively-Dropped Neural Network. CoRR abs/1807.01430 (2018) - 2017
- [j21]Feng Han, Li Li, Kun Wang, Fan Feng, Hongbing Pan, Jin Sha, Jun Lin:
An access pattern based adaptive mapping function for GPGPU scratchpad memory. IEICE Electron. Express 14(12): 20170373 (2017) - [j20]Kun Wang, Li Li, Feng Han, Fan Feng, Jun Lin, Yuxiang Fu, Jin Sha:
Optimized sorting network for successive cancellation list decoding of polar codes. IEICE Electron. Express 14(18): 20170735 (2017) - [j19]Jun Lin, Zhiyuan Yan, Zhongfeng Wang:
Efficient Soft Cancelation Decoder Architectures for Polar Codes. IEEE Trans. Very Large Scale Integr. Syst. 25(1): 87-99 (2017) - [j18]Zhisheng Wang, Jun Lin, Zhongfeng Wang:
Accelerating Recurrent Neural Networks: A Memory-Efficient Approach. IEEE Trans. Very Large Scale Integr. Syst. 25(10): 2763-2775 (2017) - [c23]Yangcan Zhou, Jun Lin, Zhongfeng Wang:
Energy efficient SVM classifier using approximate computing. ASICON 2017: 1045-1048 - [c22]Yangcan Zhou, Jun Lin, Zhongfeng Wang:
Efficient approximate layered LDPC decoder. ISCAS 2017: 1-4 - [c21]Haijian Wu, Jun Lin, Chuan Zhang, Zhongfeng Wang:
Low-complexity detection algorithms based on matrix partition for massive MIMO. WCSP 2017: 1-6 - [c20]Haochuan Zhu, Jun Lin, Zhongfeng Wang:
Reduced complexity message passing detection algorithm in large-scale MIMO systems. WCSP 2017: 1-5 - [i9]Qiong Wu, Fan Zhang, Hao Wang, Jun Lin, Yang Liu:
Parameter-free 𝓵p-Box Decoding of LDPC Codes. CoRR abs/1711.10767 (2017) - 2016
- [j17]Feng Han, Li Li, Kun Wang, Fan Feng, Hongbing Pan, Baoning Zhang, Guoqiang He, Jun Lin:
An ultra-long FFT architecture implemented in a reconfigurable application specified processor. IEICE Electron. Express 13(13): 20160504 (2016) - [j16]Kun Wang, Li Li, Feng Han, Fan Feng, Jun Lin:
Design and implementation of high performance matrix inversion based on reconfigurable processor. IEICE Electron. Express 13(15): 20160579 (2016) - [j15]Chenrong Xiong, Jun Lin, Zhiyuan Yan:
Symbol-Decision Successive Cancellation List Decoder for Polar Codes. IEEE Trans. Signal Process. 64(3): 675-687 (2016) - [j14]Jun Lin, Chenrong Xiong, Zhiyuan Yan:
A High Throughput List Decoder Architecture for Polar Codes. IEEE Trans. Very Large Scale Integr. Syst. 24(6): 2378-2391 (2016) - [j13]Chenrong Xiong, Jun Lin, Zhiyuan Yan:
A Multimode Area-Efficient SCL Polar Decoder. IEEE Trans. Very Large Scale Integr. Syst. 24(12): 3499-3512 (2016) - [c19]Chenrong Xiong, Jun Lin, Zhiyuan Yan:
Error performance analysis of the symbol-decision SC polar decoder. ICASSP 2016: 961-965 - [c18]Jun Lin, Jin Sha, Li Li, Chenrong Xiong, Zhiyuan Yan, Zhongfeng Wang:
A high throughput belief propagation decoder architecture for polar codes. ISCAS 2016: 153-156 - [c17]Jin Sha, Jun Lin, Zhongfeng Wang:
Stage-combined belief propagation decoding of polar codes. ISCAS 2016: 421-424 - [c16]Yuxiang Fu, Li Li, Hongbing Pan, Kun Wang, Feng Han, Jun Lin:
Accurate runtime thermal prediction scheme for 3D NoC systems with noisy thermal sensors. ISCAS 2016: 1198-1201 - [c15]Zhisheng Wang, Jun Lin, Zhongfeng Wang:
An Efficient Hardware Architecture for Lossless Data Compression in Data Center. SiPS 2016: 159-164 - [c14]Fangxuan Sun, Jun Lin, Zhongfeng Wang:
Intra-layer nonuniform quantization of convolutional neural network. WCSP 2016: 1-5 - [c13]Jichen Wang, Jun Lin, Zhongfeng Wang:
Efficient convolution architectures for convolutional neural network. WCSP 2016: 1-5 - 2015
- [j12]Jun Lin, Zhiyuan Yan:
An Efficient List Decoder Architecture for Polar Codes. IEEE Trans. Very Large Scale Integr. Syst. 23(11): 2508-2518 (2015) - [c12]Jun Lin, Zhiyuan Yan:
A hybrid partial sum computation unit architecture for list decoders of polar codes. ICASSP 2015: 1076-1080 - [c11]Jun Lin, Chenrong Xiong, Zhiyuan Yan:
Reduced complexity belief propagation decoders for polar codes. SiPS 2015: 1-6 - [c10]Chenrong Xiong, Jun Lin, Zhiyuan Yan:
Efficient approximate ML decoding units for polar list decoders. SiPS 2015: 1-6 - [i8]Chenrong Xiong, Jun Lin, Zhiyuan Yan:
Error Performance Analysis of the Symbol-Decision SC Polar Decoder. CoRR abs/1501.01706 (2015) - [i7]Chenrong Xiong, Jun Lin, Zhiyuan Yan:
Symbol-Decision Successive Cancellation List Decoder for Polar Codes. CoRR abs/1501.04705 (2015) - [i6]Jun Lin, Zhiyuan Yan:
A hybrid partial sum computation unit architecture for list decoders of polar codes. CoRR abs/1506.05896 (2015) - [i5]Jun Lin, Chenrong Xiong, Zhiyuan Yan:
A High Throughput List Decoder Architecture for Polar Codes. CoRR abs/1510.02574 (2015) - [i4]Jun Lin, Chenrong Xiong, Zhiyuan Yan:
Reduced Complexity Belief Propagation Decoders for Polar Codes. CoRR abs/1510.06495 (2015) - [i3]Chenrong Xiong, Jun Lin, Zhiyuan Yan:
A multi-mode area-efficient SCL polar decoder. CoRR abs/1510.07510 (2015) - 2014
- [j11]Jun Lin, Zhiyuan Yan:
An Efficient Fully Parallel Decoder Architecture for Nonbinary LDPC Codes. IEEE Trans. Very Large Scale Integr. Syst. 22(12): 2649-2660 (2014) - [j10]Jun Lin, Hongmei Xie, Zhiyuan Yan:
Efficient Error Control Decoder Architectures for Noncoherent Random Linear Network Coding. J. Signal Process. Syst. 76(2): 195-209 (2014) - [c9]Jun Lin, Zhiyuan Yan:
Efficient list decoder architecture for polar codes. ISCAS 2014: 1022-1025 - [c8]Jun Lin, Chenrong Xiong, Zhiyuan Yan:
A reduced latency list decoding algorithm for polar codes. SiPS 2014: 56-61 - [c7]Chenrong Xiong, Jun Lin, Zhiyuan Yan:
Symbol-based successive cancellation list decoder for polar codes. SiPS 2014: 198-203 - [i2]Jun Lin, Chenrong Xiong, Zhiyuan Yan:
A Reduced Latency List Decoding Algorithm for Polar Codes. CoRR abs/1405.4819 (2014) - [i1]Chenrong Xiong, Jun Lin, Zhiyuan Yan:
Symbol-Based Successive Cancellation List Decoder for Polar Codes. CoRR abs/1405.4957 (2014) - 2013
- [j9]Hongmei Xie, Jun Lin, Zhiyuan Yan, Bruce W. Suter:
Linearized Polynomial Interpolation and Its Applications. IEEE Trans. Signal Process. 61(1): 206-217 (2013) - [j8]Jun Lin, Zhiyuan Yan:
Efficient Shuffled Decoder Architecture for Nonbinary Quasi-Cyclic LDPC Codes. IEEE Trans. Very Large Scale Integr. Syst. 21(9): 1756-1761 (2013) - [c6]Jun Lin, Zhiyuan Yan:
A decoding algorithm with reduced complexity for non-binary LDPC codes over large fields. ISCAS 2013: 1688-1691 - 2012
- [j7]Xuebin Wu, Zhiyuan Yan, Jun Lin:
Reduced-Complexity Decoders of Long Reed-Solomon Codes Based on Composite Cyclotomic Fourier Transforms. IEEE Trans. Signal Process. 60(7): 3920-3925 (2012) - [c5]Jun Lin, Zhiyuan Yan:
Modified shuffled schedule for nonbinary low-density parity-check codes. ISCAS 2012: 1767-1770 - [c4]Jun Lin, Hongmei Xie, Zhiyuan Yan:
Efficient Kötter-Kschischang Decoder Architectures for Noncoherent Error Control in Random Linear Network Coding. SiPS 2012: 43-48 - 2010
- [j6]Jun Lin, Jin Sha, Zhongfeng Wang, Li Li:
An Efficient VLSI Architecture for Nonbinary LDPC Decoders. IEEE Trans. Circuits Syst. II Express Briefs 57-II(1): 51-55 (2010) - [j5]Chuan Zhang, Zhongfeng Wang, Jin Sha, Li Li, Jun Lin:
Flexible LDPC Decoder Design for Multigigabit-per-Second Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(1): 116-124 (2010) - [j4]Jun Lin, Jin Sha, Zhongfeng Wang, Li Li:
Efficient Decoder Design for Nonbinary Quasicyclic LDPC Codes. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(5): 1071-1082 (2010)
2000 – 2009
- 2009
- [j3]Jun Lin, Zhongfeng Wang, Li Li, Jin Sha, Minglun Gao:
Efficient Shuffle Network Architecture and Application for WiMAX LDPC Decoders. IEEE Trans. Circuits Syst. II Express Briefs 56-II(3): 215-219 (2009) - [j2]Jin Sha, Jun Lin, Zhongfeng Wang, Li Li, Minglun Gao:
Decoder Design for RS-Based LDPC Codes. IEEE Trans. Circuits Syst. II Express Briefs 56-II(9): 724-728 (2009) - [j1]Jin Sha, Jun Lin, Zhongfeng Wang, Li Li, Minglun Gao:
LDPC decoder design for high rate wireless personal area networks. IEEE Trans. Consumer Electron. 55(2): 455-460 (2009) - [c3]Jin Sha, Jun Lin, Li Li, Minglun Gao, Zhongfeng Wang:
LDPC Decoder Design for IEEE 802.15 Standard. ISCAS 2009: 2441-2444 - [c2]Jun Lin, Jin Sha, Zhongfeng Wang, Li Li:
An improved min-sum based column-layered decoding algorithm for LDPC codes. SiPS 2009: 238-242 - 2008
- [c1]Chuan Zhang, Li Li, Jun Lin, Zhongfeng Wang:
Low-complexity shift-LDPC decoder for high-speed communication systems. APCCAS 2008: 1636-1639
Coauthor Index
[j66] [j65] [j64] [j63] [c87] [c86] [c85] [i23] [i22] [i21] [j62] [j61] [c84] [i20] [j59] [j58] [c83] [c82] [c81] [c80] [c79] [c78] [c77] [i19] [i18] [j57] [j56] [j55] [j54] [j53] [j52] [c76] [c75] [c74] [c73] [j51] [j50] [j49] [j48] [j47] [j46] [j45] [j44] [j43] [c72] [c71] [c70] [c69] [c68] [c67] [c66] [c65] [c64] [c63] [c62] [c61] [c60] [c59] [i17] [i16] [i15] [j42] [j41] [j40] [j39] [j38] [j37] [j36] [j35] [j34] [j33] [j32] [j31] [j30] [c58] [c57] [c56] [c55] [c54] [c53] [c52] [c51] [c50] [c49] [c48] [c47] [c46] [c45] [c44] [c43] [c42] [c41] [c40] [c39] [i14] [i13] [i12] [i11] [j28] [j27] [j26] [j25] [j24] [j23] [j22] [c38] [c37] [c36] [c35] [c34] [c33] [c31] [c30] [c29] [c28] [c27] [c26] [c25] [i10] [j19] [j18] [c23] [c22] [c21] [c20] [c18] [c17] [c15] [c14] [c13] [j6] [j5] [j4] [j3] [j2] [j1] [c3] [c2] [c1]
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