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ORCIDRamprasath Srinivasa Gopalakrishnan
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- affiliation:
- affiliation (2020-2023): University of Minnesota, Minneapolis, MN, USA
- affiliation (PhD 2016): Indian Institute of Technology Madras, Department of Electrical Engineering, India
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2020 – today
- 2024
[c9]Kishor Kunal, Jitesh Poojary, S. Ramprasath
, Ramesh Harjani, Sachin S. Sapatnekar:
Automated synthesis of mixed-signal ML inference hardware under accuracy constraints. ASPDAC 2024: 478-483- [c8]Kishor Kunal, Meghna Madhusudan, Jitesh Poojary, S. Ramprasath, Arvind K. Sharma, Ramesh Harjani, Sachin S. Sapatnekar:
Reinforcing the Connection between Analog Design and EDA (Invited Paper). ASPDAC 2024: 665-670 - [d1]Hüsrev Cilasun, William Moy, Ziqing Zeng, Tahmida Islam, Hao Lo, Alex Vanasse, Megan Tan, Mohammad Anees, Ramprasath S, Abhimanyu Kumar, Sachin S. Sapatnekar, Chris H. Kim, Ulya R. Karpuzcu:
COBI: A Coupled Oscillator Based Ising Chip for Combinatorial Optimization. Zenodo, 2024
- 2023
- [j5]Sudipta Mondal, Susmita Dey Manasi, Kishor Kunal, Ramprasath S, Ziqing Zeng, Sachin S. Sapatnekar:
A Unified Engine for Accelerating GNN Weighting/Aggregation Operations, With Efficient Load Balancing and Graph-Specific Caching. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(12): 4844-4857 (2023) - [j4]Ramprasath Srinivasa Gopalakrishnan, Meghna Madhusudan, Arvind K. Sharma, Jitesh Poojary, Soner Yaldiz, Ramesh Harjani, Steven M. Burns, Sachin S. Sapatnekar:
A Generalized Methodology for Well Island Generation and Well-tap Insertion in Analog/Mixed-signal Layouts. ACM Trans. Design Autom. Electr. Syst. 28(5): 69:1-69:25 (2023) - [c7]Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Ramprasath S, Kishor Kunal, Sachin S. Sapatnekar, Ramesh Harjani:
Understanding Distance-Dependent Variations for Analog Circuits in a FinFET Technology. ESSDERC 2023: 69-72 - [c6]Sudipta Mondal, Ramprasath S, Ziqing Zeng, Kishor Kunal, Sachin S. Sapatnekar:
A Multicore GNN Training Accelerator. ISLPED 2023: 1-6 - [i1]M. Hüsrev Cilasun, Ziqing Zeng, Ramprasath S, Abhimanyu Kumar, Hao Lo, William Cho, Chris H. Kim, Ulya R. Karpuzcu, Sachin S. Sapatnekar:
3SAT on an All-to-All-Connected CMOS Ising Solver Chip. CoRR abs/2309.11017 (2023) - 2022
- [c5]Sudipta Mondal, Susmita Dey Manasi, Kishor Kunal, Ramprasath S, Sachin S. Sapatnekar:
GNNIE: GNN inference engine with load-balancing and graph-specific caching. DAC 2022: 565-570 - [c4]Tonmoy Dhar, Ramprasath S, Jitesh Poojary, Soner Yaldiz, Steven M. Burns, Ramesh Harjani, Sachin S. Sapatnekar:
A Charge Flow Formulation for Guiding Analog/Mixed-Signal Placement. DATE 2022: 148-153 - [c3]Ramprasath S, Meghna Madhusudan, Arvind K. Sharma, Jitesh Poojary, Soner Yaldiz, Ramesh Harjani, Steven M. Burns, Sachin S. Sapatnekar:
Analog/Mixed-Signal Layout Optimization using Optimal Well Taps. ISPD 2022: 159-166
2010 – 2019
- 2016
- [j3]Ramprasath S, Vinita Vasudevan:
Efficient Algorithms for Discrete Gate Sizing and Threshold Voltage Assignment Based on an Accurate Analytical Statistical Yield Gradient. ACM Trans. Design Autom. Electr. Syst. 21(4): 66:1-66:27 (2016) - [j2]Ramprasath S, Madiwalar Vijaykumar, Vinita Vasudevan:
A Skew-Normal Canonical Model for Statistical Static Timing Analysis. IEEE Trans. Very Large Scale Integr. Syst. 24(6): 2359-2368 (2016) - 2015
- [c2]S. Ramprasath, Vinita Vasudevan:
An efficient algorithm for statistical timing yield optimization. DAC 2015: 166:1-166:6 - 2014
- [j1]S. Ramprasath, Vinita Vasudevan:
Statistical Criticality Computation Using the Circuit Delay. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(5): 717-727 (2014) - 2012
- [c1]S. Ramprasath, Vinita Vasudevan:
On the computation of criticality in statistical timing analysis. ICCAD 2012: 172-179
Coauthor Index
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