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ORCIDXin Xin 0008
Person information
- affiliation: University of Central Florida, FL, USA
- affiliation (former): University of Pittsburgh, PA, USA
- affiliation (former): Tsinghua University, China
Other persons with the same name
- Xin Xin — disambiguation page
- Xin Xin 0001 — Beijing Institute of Technology, Beijing School of Computer Science and Technology, China
- Xin Xin 0002 — Chinese University of Hong Kong, Department of Computer Science and Engineering, Hong Kong
- Xin Xin 0003
![[0000-0001-6116-9115]](https://dblp.uni-trier.de./img/orcid-mark.12x12.png "0000-0001-6116-9115")
— Shandong University, Information Retrieval Lab, School of Computer Science and Technology, China (and 2 more) - Xin Xin 0004 — Okayama Prefectural University, Faculty of Computer Science and Systems Engineering, Japan
- Xin Xin 0005 — Xi'an University of Posts and Telecommunications, School of Electronics Engineering, China
- Xin Xin 0006 — Beijing Normal University, Faculty of Psychology, China
- Xin Xin 0007 — University of Glasgow, School of Computing Science, UK (and 1 more)
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2020 – today
- 2024
[c9]Weidong Cao, Jian Gao, Xin Xin, Xuan Zhang:
Addition is Most You Need: Efficient Floating-Point SRAM Compute-in-Memory by Harnessing Mantissa Addition. DAC 2024: 156:1-156:6- 2023
- [c8]Yanan Guo, Dingyuan Cao, Xin Xin, Youtao Zhang, Jun Yang:
Uncore Encore: Covert Channels Exploiting Uncore Frequency Scaling. MICRO 2023: 843-855 - 2022
- [c7]Xin Xin, Wanyi Zhu, Li Zhao:
Architecting DDR5 DRAM caches for non-volatile memory systems. DAC 2022: 1057-1062 - [c6]Yanan Guo, Xin Xin, Youtao Zhang, Jun Yang:
Leaky Way: A Conflict-Based Cache Covert Channel Bypassing Set Associativity. MICRO 2022: 646-661 - 2021
- [c5]Congming Gao, Xin Xin, Youyou Lu, Youtao Zhang, Jun Yang, Jiwu Shu:
ParaBit: Processing Parallel Bitwise Operations in NAND Flash Memory based SSDs. MICRO 2021: 59-70 - [c4]Xin Xin, Yanan Guo, Youtao Zhang, Jun Yang:
SAM: Accelerating Strided Memory Accesses. MICRO 2021: 324-336 - 2020
- [c3]Xin Xin, Youtao Zhang, Jun Yang:
Reducing DRAM Access Latency via Helper Rows. DAC 2020: 1-6 - [c2]Xin Xin, Youtao Zhang, Jun Yang:
ELP2IM: Efficient and Low Power Bitwise Operation Processing in DRAM. HPCA 2020: 303-314
2010 – 2019
- 2019
- [c1]Xin Xin, Youtao Zhang, Jun Yang:
ROC: DRAM-based Processing with Reduced Operation Cycles. DAC 2019: 29
Coauthor Index
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