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ORCIDHari Cherupalli
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2020 – today
- 2024
[c11]Yinghua Hu
, Hari Cherupalli, Mike Borza, Deepak D. Sherlekar:
Late Breaking Results: On the One-Key Premise of Logic Locking. DAC 2024: 355:1-355:2- [i1]Yinghua Hu, Hari Cherupalli, Mike Borza, Deepak D. Sherlekar:
Late Breaking Results: On the One-Key Premise of Logic Locking. CoRR abs/2408.12690 (2024) - 2022
- [c10]Subhash Sethumurugan, Shashank Hegde, Hari Cherupalli, John Sartori:
A scalable symbolic simulation tool for low power embedded systems. DAC 2022: 175-180 - 2021
- [c9]Shashank Hegde, Subhash Sethumurugan, Hari Cherupalli, Henry Duwe, John Sartori:
Constrained Conservative State Symbolic Co-analysis for Ultra-low-power Embedded Systems. ASP-DAC 2021: 318-324
2010 – 2019
- 2018
- [j2]Hari Cherupalli, Henry Duwe, Weidong Ye, Rakesh Kumar, John Sartori:
Bespoke Processors for Applications with Ultra-Low Area and Power Constraints. IEEE Micro 38(3): 32-39 (2018) - 2017
- [j1]Hari Cherupalli, Henry Duwe, Weidong Ye, Rakesh Kumar, John Sartori:
Determining Application-Specific Peak Power and Energy Requirements for Ultra-Low-Power Processors. ACM Trans. Comput. Syst. 35(3): 9:1-9:33 (2017) - [c8]Hari Cherupalli, Henry Duwe, Weidong Ye, Rakesh Kumar, John Sartori:
Determining Application-specific Peak Power and Energy Requirements for Ultra-low Power Processors. ASPLOS 2017: 3-16 - [c7]Hari Cherupalli, Henry Duwe, Weidong Ye, Rakesh Kumar, John Sartori:
Enabling Effective Module-Oblivious Power Gating for Embedded Processors. HPCA 2017: 157-168 - [c6]Hari Cherupalli, John Sartori:
Scalable N-worst algorithms for dynamic timing and activity analysis. ICCAD 2017: 585-592 - [c5]Hari Cherupalli, Henry Duwe, Weidong Ye, Rakesh Kumar, John Sartori:
Bespoke Processors for Applications with Ultra-low Area and Power Constraints. ISCA 2017: 41-54 - [c4]Hari Cherupalli, Henry Duwe, Weidong Ye, Rakesh Kumar, John Sartori:
Software-based gate-level information flow security for IoT systems. MICRO 2017: 328-340 - 2016
- [c3]Amrut Kapare, Hari Cherupalli, John Sartori:
Automated error prediction for approximate sequential circuits. ICCAD 2016: 82 - [c2]Hari Cherupalli, Rakesh Kumar, John Sartori:
Exploiting Dynamic Timing Slack for Energy Efficiency in Ultra-Low-Power Embedded Systems. ISCA 2016: 671-681 - 2015
- [c1]Hari Cherupalli, John Sartori:
Graph-based Dynamic Analysis: Efficient Characterization of Dynamic Timing and Activity Distributions. ICCAD 2015: 729-735
Coauthor Index
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