"Dyn-Bitpool: A Two-sided Sparse CIM Accelerator Featuring a Balanced ..."

Xujiang Xiang et al. (2024)

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DOI: 10.1145/3649329.3655690

access: closed

type: Conference or Workshop Paper

metadata version: 2024-11-30

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Xujiang Xiang, Zhiheng Yue, Yuxuan Li, Liuxin Lv, Shaojun Wei, Yang Hu, Shouyi Yin:
Dyn-Bitpool: A Two-sided Sparse CIM Accelerator Featuring a Balanced Workload Scheme and High CIM Macro Utilization. DAC 2024: 35:1-35:6

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