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2020 – today
- 2021
[j6]Yinan Zhao
, Jinwu Zhuang, Zhihao Ye, Zhiliang Qian, Fang Peng:
Simulation of Steady-State Temperature Rise of Electric Heating Field of Wireless Sensor Circuit Fault Current Trigger. J. Sensors 2021: 1-11 (2021)
2010 – 2019
- 2019
- [j5]Wei Gao, Zhiliang Qian, Pingqiang Zhou:
Reliability- and performance-driven mapping for regular 3D NoCs using a novel latency model and Simulated Allocation. Integr. 65: 351-361 (2019) - 2017
- [c17]Jingyang Zhu, Zhiliang Qian, Chi-Ying Tsui:
BHNN: A memory-efficient accelerator for compressing deep neural networks with blocked hashing techniques. ASP-DAC 2017: 690-695 - [c16]Da-Cheng Juan, Neil Shah, Mingyu Tang, Zhiliang Qian, Diana Marculescu, Christos Faloutsos:
M3A: Model, MetaModel and Anomaly Detection for Inter-arrivals of Web Searches and Postings. DSAA 2017: 341-350 - 2016
- [j4]Jingyang Zhu, Zhiliang Qian, Chi-Ying Tsui:
BiLink: A high performance NoC router architecture using bi-directional link with double data rate. Integr. 55: 30-42 (2016) - [j3]Zhiliang Qian, Da-Cheng Juan, Paul Bogdan, Chi-Ying Tsui, Diana Marculescu, Radu Marculescu:
A Support Vector Regression (SVR)-Based Latency Model for Network-on-Chip (NoC) Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(3): 471-484 (2016) - [j2]Zhiliang Qian, Paul Bogdan, Chi-Ying Tsui, Radu Marculescu:
Performance Evaluation of NoC-Based Multicore Systems: From Traffic Analysis to NoC Latency Modeling. ACM Trans. Design Autom. Electr. Syst. 21(3): 52:1-52:38 (2016) - [c15]Jingyang Zhu, Zhiliang Qian, Chi-Ying Tsui:
LRADNN: High-throughput and energy-efficient Deep Neural Network accelerator using Low Rank Approximation. ASP-DAC 2016: 581-586 - [c14]Bo Liang, Kefeng Duan, Qingsong Xie, Mohamed Atef, Zhiliang Qian, Guoxing Wang, Yong Lian:
Live demonstration: A support vector machine based hardware platform for blood pressure prediction. BioCAS 2016: 130 - [c13]Weiwei Shi, Yongxin Zhu, Philip S. Yu, Mengyun Liu, Guoxing Wang, Zhiliang Qian, Yong Lian:
Incomplete electrocardiogram time series prediction. BioCAS 2016: 200-203 - [c12]Kefeng Duan, Yufei Hu, Zhiliang Qian, Guoxing Wang:
An FPGA-based morphological filter for baseline wandering correction in photoplethysmography. BioCAS 2016: 216-219 - [c11]Kefeng Duan, Zhiliang Qian, Mohamed Atef, Guoxing Wang:
A feature exploration methodology for learning based cuffless blood pressure measurement using photoplethysmography. EMBC 2016: 6385-6388 - [i2]Da-Cheng Juan, Neil Shah, Mingyu Tang, Zhiliang Qian, Diana Marculescu, Christos Faloutsos:
M3A: Model, MetaModel, and Anomaly Detection in Web Searches. CoRR abs/1606.05978 (2016) - 2015
- [j1]Zhiliang Qian, Syed Mohsin Abbas, Chi-Ying Tsui:
FSNoC: A Flit-Level Speedup Scheme for Network on-Chips Using Self-Reconfigurable Bidirectional Channels. IEEE Trans. Very Large Scale Integr. Syst. 23(9): 1854-1867 (2015) - 2014
- [c10]Zhiliang Qian, Da-Cheng Juan, Paul Bogdan, Chi-Ying Tsui, Diana Marculescu, Radu Marculescu:
A comprehensive and accurate latency model for Network-on-Chip performance analysis. ASP-DAC 2014: 323-328 - [c9]Yuankun Xue, Zhiliang Qian, Paul Bogdan, Fan Ye, Chi-Ying Tsui:
Disease Diagnosis-on-a-Chip: Large Scale Networks-on-Chip based Multicore Platform for Protein Folding Analysis. DAC 2014: 104:1-104:6 - [c8]Yuankun Xue, Zhiliang Qian, Guopeng Wei, Paul Bogdan, Chi-Ying Tsui, Radu Marculescu:
An efficient Network-on-Chip (NoC) based multicore platform for hierarchical parallel genetic algorithms. NOCS 2014: 17-24 - [i1]Zhiliang Qian:
High Performance Network-on-Chips (NoCs) Design: Performance Modeling, Routing Algorithm and Architecture Optimization. CoRR abs/1406.3790 (2014) - 2013
- [c7]Zhiliang Qian, Da-Cheng Juan, Paul Bogdan, Chi-Ying Tsui, Diana Marculescu, Radu Marculescu:
SVR-NoC: a performance analysis tool for network-on-chips using learning-based support vector regression model. DATE 2013: 354-357 - [c6]Zhiliang Qian, Paul Bogdan, Chi-Ying Tsui, Radu Marculescu:
Performance evaluation of multicore systems: from traffic analysis to latency predictions (embedded tutorial). ICCAD 2013: 82-84 - 2012
- [c5]Zhiliang Qian, Paul Bogdan, Guopeng Wei, Chi-Ying Tsui, Radu Marculescu:
A traffic-aware adaptive routing algorithm on a highly reconfigurable network-on-chip architecture. CODES+ISSS 2012: 161-170 - [c4]Zhiliang Qian, Ying Fei Teh, Chi-Ying Tsui:
A flit-level speedup scheme for network-on-chips using self-reconfigurable bi-directional channels. DATE 2012: 1295-1300 - 2011
- [c3]Zhiliang Qian, Chi-Ying Tsui:
A thermal-aware application specific routing algorithm for Network-on-Chip design. ASP-DAC 2011: 449-454 - [c2]Zhiliang Qian, Ying Fei Teh, Chi-Ying Tsui:
A fault-tolerant network-on-chip design using dynamic reconfiguration of partial-faulty routing resources. VLSI-SoC 2011: 192-195 - [c1]Ying Fei Teh, Zhiliang Qian, Chi-Ying Tsui:
A fault-tolerant NoC using combined link sharing and partial fault link utilization scheme. VLSI-SoC 2011: 296-301
Coauthor Index
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