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2020 – today
- 2025
[j10]Jie Ding
, Fuming Liu, Kuan Deng, Zihan Zheng, Jingnan Zheng, Yongzhen Chen, Jiangfeng Wu:
A 16-bit 1-MS/s SAR ADC With Capacitor Mismatch Self-Calibration. IEEE Trans. Very Large Scale Integr. Syst. 33(1): 10-20 (2025)- 2024
- [j9]Zihan Zheng, Yongzhen Chen, Jie Ding, Xinhao Xu, Kuan Deng, Yangxin Xiang, Weibo Li, Jiangfeng Wu:
Design and Implementation of an EMI-Immune Daisy Chain Interface With a PID-Based CDR Algorithm for Battery Management System Communication. IEEE Access 12: 126438-126445 (2024) - [j8]Huajun Yao, Yangxin Xiang, Yongzhen Chen, Jiangfeng Wu:
A Foreground Wide-Band Receiver I/Q Mismatch Calibration Method in FDD Transceiver. IEEE Trans. Circuits Syst. I Regul. Pap. 71(6): 2590-2599 (2024) - [j7]Yangxin Xiang, Huajun Yao, Minghao Jiang, Junkun Chen, Yongzhen Chen, Jiangfeng Wu:
A 0.5-V 0.02% THD Bulk-Driven OTA for Continuous-Time Applications in 180 nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 71(10): 4420-4433 (2024) - [c44]Mingzhe Liu, Yongzhen Chen, Jiangfeng Wu, Cuixia Wang:
A 40Gb/s Multi-band Wireline Receiver Analog Front-end for 50.4dB Channel Loss Compensation. MWSCAS 2024: 1-5 - 2023
- [j6]Xiaoping Xie, Yongzhen Chen, Rufeng Shen, Dan Tian:
Research on monaural speech segregation based on feature selection. EURASIP J. Audio Speech Music. Process. 2023(1): 10 (2023) - [c43]Jun Chen, Fengyi Mei, Mingzhe Liu, Yongzhen Chen, Jiangfeng Wu:
A 32GS/s 7bit TI-SAR ADC in 28nm for 32Gb/s ADC-Based SerDes Receiver. ASICON 2023: 1-4 - [c42]Weibo Li, Minghao Jiang, Yongzhen Chen, Jiangfeng Wu:
Complexity-Reduced Joint Calibration for Nonlinearity and I/Q Imbalance in Direct-Conversion Transmitters. ASICON 2023: 1-4 - [c41]Hang Ling, Yifei Bai, Fengyi Mei, Huajun Yao, Yongzhen Chen, Jiangfeng Wu:
Pipelined-SAR ADC Calibration Technique Based on Gain-Bit Weights. ASICON 2023: 1-4 - [c40]Xinhao Xu, Yongzhen Chen, Jiangfeng Wu:
A low-power daisy-chain controller implemention in BMS based on power mode switching. ASICON 2023: 1-4 - [c39]Jiangshan Zhao, Jiankun Huang, Yongzhen Chen, Jiangfeng Wu:
A Low-power Digital Automatic Gain Control Design in Wireless Communication Receivers. ASICON 2023: 1-4 - [c38]Yiwei Zhou, Weibo Li, Yongzhen Chen:
Nonlinear modeling of MIMO antenna array power amplifiers based on time-delay neural network. ASICON 2023: 1-4 - [c37]Junkun Chen, Youzhi Gu, Miaomiao Xu, Yongzhen Chen, Cuixia Wang, Jiangfeng Wu:
A 4.75-64 Gb/s PAM-4 Wireline Transmitter with 3-tap FFE in 28-nm CMOS. ISCAS 2023: 1-5 - [c36]Jie Ding, Yongzhen Chen, Cuixia Wang, Jiangfeng Wu:
A Foreground LSB-Based Capacitor Mismatch Calibration Method in An 18-bit SAR ADC. ISCAS 2023: 1-5 - [c35]Huajun Yao, Yangxin Xiang, Yongzhen Chen, Cuixia Wang, Jiangfeng Wu:
A Wideband Receiver I/Q Mismatch Calibration Method in FDD Transceiver. ISCAS 2023: 1-4 - 2022
- [j5]Jingchao Lan, Yongzhen Chen, Xingchen Shen, Zhekan Ni, Yimin Wu, Fan Ye, Junyan Ren:
Effective Gain Analysis and Statistic Based Calibration for Ring Amplifier With Robustness to PVT Variation. IEEE Trans. Circuits Syst. II Express Briefs 69(2): 304-308 (2022) - [c34]Minghao Jiang, Chenyang Han, Weibo Li, Jiangfeng Wu, Yongzhen Chen:
0.7-6 GHz Programable Gain Push-Pull Driver PA Based on Dual-Loop Biases. APCCAS 2022: 213-216 - [c33]Xinjie Feng, Yongzhen Chen, Youzhi Gu, Jiangfeng Wu:
A 64Gb/s PAM-4 Digital Equalizer With Tap-Configurable FFE and Partially Unrolled DFE in 28nm CMOS. ICTA 2022: 162-163 - [c32]Jingchao Lan, Danfeng Zhai, Yongzhen Chen, Zhekan Ni, Xingchen Shen, Fan Ye, Junyan Ren:
A 2.5-GS/s Time-Interleaved SAR-Assisted Ringamp-Based Pipelined ADC with Digital Background Calibration. ISCAS 2022: 2655-2659 - [c31]Yangxin Xiang, Chenyang Han, Cuixia Wang, Jiangfeng Wu, Yongzhen Chen:
A Current-Mode, 30 dB Range with 0.5 dB Step, 0.1 to 6 GHz Attenuator for Wideband Receiver. MWSCAS 2022: 1-4 - [c30]Xinghui Zhu, Yongzhen Chen, Xiaodong Zhang, Zhiwei Zhang, Baoquan Ren:
Feature Matching for Indoor-Oriented Visual Odometry. NaNA 2022: 253-258 - 2021
- [j4]Yuefeng Cao, Shumin Zhang, Tianli Zhang, Yongzhen Chen, Yutong Zhao, Chixiao Chen, Fan Ye, Junyan Ren:
A 91.0-dB SFDR Single-Coarse Dual-Fine Pipelined-SAR ADC With Split-Based Background Calibration in 28-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 68(2): 641-654 (2021) - [c29]Jiankun Huang, Xinjie Feng, Congying Zhou, Yongzhen Chen:
A High-Performance Mel-scale Frequency Cepstral Coefficients Digital Circuit Used on Keyword-Spotting Chip. ASICON 2021: 1-4 - [c28]Xiaozhe Wang, Lingzhi Su, Xiyuan Du, Yongzhen Chen, Jiangfeng Wu:
Physical Coding Sublayer For 32Gbps SerDes Based On JESD204C. ASICON 2021: 1-4 - [c27]Yunchuan Wang, Li Zhang, Fengyi Mei, Yongzhen Chen, Jiangfeng Wu:
Digital Calibration of Capacitor Mismatch and Gain Error in Pipelined SAR ADCs. ASICON 2021: 1-4 - [c26]Yujie Wu, Gang Zhang, Yongzhen Chen, Jiangfeng Wu:
A 6-bit Active Phase Shifter with Quadrature Outputs. ASICON 2021: 1-4 - [c25]Li Zhang, Yunchuan Wang, Fengyi Mei, Yongzhen Chen, Jiangfeng Wu:
An Input Buffer for 4 GS/s 14-b Time-Interleaved ADC. ASICON 2021: 1-4 - [c24]Runze Chi, Junkun Chen, Youzhi Gu, Jiangfeng Wu, Yongzhen Chen:
A 161mW 32Gb/s ADC-Based NRZ SerDes Receiver Front End in 28nm. ICTA 2021: 10-11 - [c23]Liran Dong, Yujun Shu, Yongzhen Chen, Jiangfeng Wu:
A 2-GS/s 200-MHz BW Oversampling Continuous-Time Pipeline ADC with Adaptive Digital Filter in 28nm. ICTA 2021: 245-246 - [c22]Yangxin Xiang, Saisai Jin, Yongzhen Chen, Jiangfeng Wu:
A 71dB DC Gain, 0.1% THD, 0.5-V Bulk-Driven Class-AB OTA Achieved by Novel CMFB Methods. MWSCAS 2021: 6-9 - [c21]Youzhi Gu, Junkun Chen, Xiaolin Li, Yongzhen Chen, Jiangfeng Wu:
A 32Gb/s NRZ Wireline Transmitter with CMFB- Based CML Driver in 28nm CMOS Technology. MWSCAS 2021: 14-17
2010 – 2019
- 2019
- [j3]Zhekan Ni, Yongzhen Chen, Fan Ye, Junyan Ren:
A 7.8 fJ/conversion-step 9-bit 400-MS/s single-channel SAR ADC with fast control logic. Microelectron. J. 84: 59-66 (2019) - [c20]Yongzhen Chen, Jiangfeng Wu:
High Linear Ring Amplifier Design with Analysis on Settling Procedures. ASICON 2019: 1-4 - [c19]Qi Li, Yujun Shu, Yongzhen Chen, Jiangfeng Wu:
An Area-Efficient Multi-Rate Digital Decimator. ASICON 2019: 1-4 - [c18]Pingshun Ma, Yongzhen Chen, Jiangfeng Wu:
A Double-Latch Comparator for Multi-GS/s SAR ADCs in 28nm CMOS. ASICON 2019: 1-3 - [c17]Yongzhen Chen, Xingchen Shen, Zhekan Ni, Jingchao Lan, Chixiao Chen, Fan Ye, Junyan Ren:
A 625MS/s, 12-Bit, SAR Assisted Pipeline ADC with Effective Gain Analysis for Inter-stage Ringamps. ESSCIRC 2019: 197-200 - 2018
- [j2]Yongzhen Chen, Fan Ye, Junyan Ren:
An 8.2 fJ/conversion-step 9-bit 135 MS/s SAR ADC with redundant methods for acceleration. Microelectron. J. 73: 52-58 (2018) - [j1]Yongzhen Chen, Jingjing Wang, Hang Hu, Fan Ye, Junyan Ren:
A Time-Interleaved SAR Assisted Pipeline ADC With a Bias-Enhanced Ring Amplifier. IEEE Trans. Circuits Syst. II Express Briefs 65-II(11): 1584-1588 (2018) - [c16]Yuefeng Cao, Yongzhen Chen, Zhekan Ni, Fan Ye, Junyan Ren:
An 11b 80MS/s SAR ADC With Speed-Enhanced SAR Logic and High-Linearity CDAC. APCCAS 2018: 18-21 - [c15]Zhekan Ni, Yongzhen Chen, Fan Ye, Junyan Ren:
A 7.8 fJ/conversion-step 9-bit 400-MS/s single-channel SAR ADC with fast control logic. APCCAS 2018: 42-45 - [c14]Yuefeng Cao, Tianli Zhang, Yongzhen Chen, Fan Ye, Junyan Ren:
An Operational Amplifier Assisted Input Buffer and An Improved Bootstrapped Switch for High-Speed and High-Resolution ADCs. ISCAS 2018: 1-5 - [c13]Yongzhen Chen, Zhekan Ni, Yuefeng Cao, Fan Ye, Junyan Ren:
A 800 MS/s, 12-Bit, Ringamp-Based SAR assisted Pipeline ADC with Gain Error Cancellation. ISCAS 2018: 1-4 - [c12]Manxin Li, Yongzhen Chen, Fan Ye, Junyan Ren:
A 100MS/S 12-bit Coarse-Fine SAR ADC with Shared Split-CDAC. ISCAS 2018: 1-4 - [c11]Zhiyuan Dai, Hang Hu, Yongzhen Chen, Fan Ye, Junyan Ren:
A 12-Bit ENOB 8MHz BW Noise-Shaping SAR ADC Using High-Speed Switches. MWSCAS 2018: 392-395 - 2017
- [c10]Yimin Wu, Yongzhen Chen, Manxin Li, Fan Ye, Junyan Ren:
A stacked-packaged 16-channel ADC for ultrasound application. ASICON 2017: 245-248 - [c9]Yongzhen Chen, Yimin Wu, Fubiao Cao, Fan Ye, Junyan Ren:
A background time-skew calibration technique in flash-assisted time-interleaved SAR ADCs. ASICON 2017: 295-298 - [c8]Fubiao Cao, Yongzhen Chen, Zhiyuan Dai, Fan Ye, Junyan Ren:
An input buffer for 12bit 2GS/s ADC. ASICON 2017: 750-753 - [c7]Fubiao Cao, Yongzhen Chen, Yuefeng Cao, Fan Ye, Junyan Ren:
A proved dither-injection method for memory effect in double sampling pipelined ADC. ASICON 2017: 754-757 - [c6]Yongzhen Chen, Jingjing Wang, Hang Hu, Fan Ye, Junyan Ren:
A 200MS/s, 11 bit SAR-assisted pipeline ADC with bias-enhanced ring amplifier. ISCAS 2017: 1-4 - [c5]Yuefeng Cao, Yongzhen Chen, Tianli Zhang, Fan Ye, Junyan Ren:
An improved ring amplifier with process- and supply voltage-insensitive dead-zone. MWSCAS 2017: 811-814 - 2015
- [c4]Rongjin Xu, Yongzhen Chen, Mingshuo Wang, Ning Li, Fan Ye, Junyan Ren:
A 1.5-GS/s 5-bit interpolating ADC with offset averaging and interpolating sharing resistors network. ASICON 2015: 1-4 - [c3]Shunli Ma, Guangyao Zhou, Jianbing Jiang, Chixiao Chen, Yongzhen Chen, Fan Ye, Junyan Ren:
A quadrature clock generator with calibration for 22∼31.4 GS/s real-time sampling system. ESSCIRC 2015: 136-139 - 2013
- [c2]Yongzhen Chen, Chixiao Chen, Qiang Zhang, Fan Ye, Junyan Ren:
A 12-bit 200-MS/s sample-and-hold amplifier with a hybrid Miller-Feedforward compensation technique. ASICON 2013: 1-4 - [c1]Yongzhen Chen, Miguel Rodel Felipe, Yi Wang, Yajun Ha, Shu Qin Ren, Khin Mi Mi Aung:
sAES: A high throughput and low latency secure cloud storage with pipelined DMA based PCIe interface. FPT 2013: 374-377
Coauthor Index
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