"Parallel implementations of SHA-3 on a 24-core processor with software and ..."

Jianwei Yang et al. (2017)

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DOI: 10.1109/ASICON.2017.8252635

access: closed

type: Conference or Workshop Paper

metadata version: 2018-08-28

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Jianwei Yang, Weizhen Wang, Zhicheng Xie, Jun Han, Zhiyi Yu, Xiaoyang Zeng:
Parallel implementations of SHA-3 on a 24-core processor with software and hardware co-design. ASICON 2017: 953-956

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