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ORCIDA-SSCC 2023: Haikou, China
- IEEE Asian Solid-State Circuits Conference, A-SSCC 2023, Haikou, China, November 5-8, 2023. IEEE 2023, ISBN 979-8-3503-3003-8
- Shuang Wang, Weiliang Chen, Xueqing Li, Leibo Liu, Huazhong Yang:
A 10TFLOPS Datacenter-Oriented GPU with 4-Corner Stacked 64GB Memory by The Means of 2.5D Packaging Technology. 1-3 - Yidan Zhang, Zhao Zhang, Yiqing Xu, Xinyu Shen, Nan Qi, Nanjian Wu, Jian Liu, Liyuan Liu:
A Wideband Low-Noise Linear LiDAR Analog Front-End Achieving 1.6 GHz Bandwidth, $\boldsymbol{2.7}\ \mathbf{pA}/\mathbf{Hz}^{\boldsymbol{0.5}}$ Input Referred Noise, and 103 $\mathbf{dB}\mathbf{\Omega}$ Transimpedance Gain. 1-3 - Hyun-Su Lee, Hyung-Min Lee:
A 92.7%-Efficiency 6.78-MHz Dual-Output Energy-Resuscitating Resonant Regulating Rectifier for Wirelessly Powered Systems. 1-3 - Pingda Guan
, Haikun Jia, Wei Deng, Ruichang Ma, Mingxing Deng, Jiamin Xue, Angxiao Yan, Shiyan Sun, Zhihua Wang, Baoyong Chi:
A Fully Integrated Bit-to-Bit 24/48Gb/s QPSK/16-QAM D-Band Transceiver with Mixed-Signal Baseband in 28nm CMOS Technology. 1-3 - Jie Zhou, Changxuan Han, Wen Chen, Bingzheng Yang, Xun Luo:
A 71-to-86GHz, 20.4dBm $\mathbf{P}_{\mathbf{out}}$, 6.0dB NF Transceiver with Quadrature Direct-Modulated Transmitter and Reflection-Less Heterodyne Receiver in 40nm CMOS. 1-3 - Han Liu, Nan Qi, Donglai Lu, Zizheng Dong, Zhihan Zhang, Jian He, Guike Li, Leliang Li, Ye Liu, Ziyue Dang, Daigao Chen, Zhao Zhang, Jian Liu, Nanjian Wu, Xi Xiao, Liyuan Liu:
A $\boldsymbol{4} \times \boldsymbol{112}-\mathbf{Gb}/\mathbf{s}$ PAM-4 Silicon-Photonic Transceiver Front-End for Linear-Drive Co-Packaged Optics. 1-3 - Aobo Li, Jiahao Lu, Dongsheng Liu, Xiang Li, Shuo Yang, Tianze Huang, Jiaming Zhang, Siqi Xiong, Chenjun Yang:
A 40nm $\boldsymbol{2.76}\boldsymbol{\mu}\mathbf{J}/\mathbf{Op}$ Energy-Efficient Secure Post-Quantum Crypto-Processor for Crystals-Kyber on Module-LWE. 1-3 - Leibo Liu:
Welcome Message. 1-2 - Angxiao Yan, Wei Deng, Haikun Jia, Shiwei Zhang, Baoyong Chi:
A Transient Enhancement Digital LDO with Adaptive Ripple Cancelation Based on Optimal Compensation Period Approximation. 1-3 - Shun Yamaguchi, Takashi Hisakado, Osami Wada, Mahfuzul Islam:
An Adaptive-Sampling Digital LDO with Statistical Comparator Selection Achieving 99.99% Maximum Current Efficiency and 0.25ps FoM in 65nm. 1-3 - Bu-Il Nam, Jayang Yoon, Kyunghea Lee, Sol Kim, Junhong Park, Chiweon Yoon, Eunkyoung Kim:
Integrated Circuit to Compensate Parasitic Leakage Component for WL Leakage Current in NAND Flash Memory. 1-3 - Seunghoon Lee, Junhyeong Kim, Ho-Jin Song:
248 GHz Compact Mixer-Last Direct-Conversion Transmitter with I/Q Imbalance and LO Feedthrough Calibration Capability. 1-3 - Yongjo Kim, Taekwang Jang, SeongHwan Cho:
A Jitter-Programmable Bang-Bang Phase-Locked Loop Using PVT Invariant Stochastic Jitter Monitor. 1-3 - Xiaodong Meng, Xing Li, Yuan Yao, Chi-Ying Tsui, Wing-Hung Ki:
A Primary Driver with Real-Time Resonance Tracking for Wireless-Powered Implantable Medical Devices. 1-3 - Chih-Ming Hung:
Semiconductor Chip Design in a Legoland. 1-4 - Zeli Li, Tianrui Lyu, Kaiyou Li, Haoxin Zheng, Zhuohang Ye, Shengzhao Su, Jianping Guo, Yang Liu:
An 80-dB Dynamic Range Hybrid Pulse-Phase Analog Front-End Circuit Cooperating With a Low-Resolution TDC for LiDAR. 1-3 - Qiaobo Ma, Huihua Li, Xiongjie Zhang, Anyang Zhao, Yang Jiang, Man-Kay Law, Rui Paulo Martins, Pui-In Mak:
A Cross-Coupled Hybrid SC Converter with Extended VCR Range and Intrinsic Loss Balance Achieving 90% Average Efficiency with 1.5% Variation Over Full Li-ion Battery Input Range and 0.95A/mm2 Peak Current Density. 1-3 - Jingsen Yang, Liangjian Lyu, Zirui Dong, Heyu Ren, Chuanjin Richard Shi:
A 28-nW Noise-Robust Voice Activity Detector with Background Aware Feature Extraction. 1-3 - Xiangrong Huang, Haikun Jia, Wei Deng, Zhihua Wang, Baoyong Chi:
A Compact E-Band Load-Modulation Balanced Power Amplifier Using Coupled Transmission-Line Output Network Achieving 22.1-dBm Psat and 34.9%/12.2% Efficiency at Psat/6-dB PBO. 1-3 - Weiquan Hao, Xunyu Li, Zijin Pan, Runyu Miao, Albert Z. Wang:
ESD Protection is About Circuit Design: Practices and Perspectives. 1-3 - Hedi Wang, Zengwei Wang, Yaolei Li, Chen Tang, Jinxu Gao, Huazhong Yang, Yongpan Liu:
A 28nm 386.5GOPS/W Coarse-Grained DSP Using Configurable Processing Elements for Always-on Computation with FPGA Implementation. 1-3 - Ruiqi Guo, Yang Wang, Xiaofeng Chen, Lei Wang, Hao Sun, Jingchuan Wei, Leibo Liu, Shaojun Wei, Yang Hu, Shouyi Yin:
CIMFormer: A 38.9TOPS/W-8b Systolic CIM-Array Based Transformer Processor with Token-Slimmed Attention Reformulating and Principal Possibility Gathering. 1-3 - Shea Smith, Taylor Barton, Yen-Cheng Kuan, Armin Tajalli, Mau-Chung Frank Chang, Shiuh-Hua Wood Chiang:
A 0.12-V 200-Hz-BW 10-Bit ADC Using Quad-Channel VCO and Interpolation Linearization. 1-3 - Yuncheng Lu, Xin Zhang, Zehao Li, Bo Wang, Tony Tae-Hyoung Kim:
SESOMP: A Scalable and Energy-Efficient Self-Organizing Map Processor with Computing-In-Memory and Dead Neuron Pruning. 1-3 - Jingu Lee, Sangjin Kim, Wooyoung Jo, Hoi-Jun Yoo:
An Energy-Efficient Heterogeneous Fourier Transform-Based Transformer Accelerator with Frequency-Wise Dynamic Bit-Precision. 1-3 - Gichan Yun, Kyeongwon Jeong, Haidam Choi, Seunghyeon Nam, Chaerin Oh, Hyunjoo Jenny Lee, Sohmyung Ha, Minkyu Je:
A 2pA/√Hz Current-Conveyor-Assisted Ultrasound Receiver with 25pF CMUT Parasitic Capacitance. 1-3 - Jiangchao Wu, Guangshu Zhao, Litao Zhang, Yu Jia, Yang Jiang, Pui-In Mak, Rui Paulo Martins, Man Kay Law:
Fully Integrated Reconfigurable Solar Energy Harvester for $100\mu\mathrm{A}$ Burst Output Current Delivery with 78.6% Peak Energy Extraction Efficiency and Minimum Startup Incident Light Power of 0.27mW/cm2. 1-3 - Tengxiao Wang, Min Tian, Zhengqing Zhong, Haibing Wang, Junxian He, Fang Tang, Xichuan Zhou, Shuangming Yu, Nanjian Wu, Liyuan Liu, Cong Shi:
MorphBungee: A 65nm 7.2mm2 27μJ/image Digital Edge Neuromorphic Chip with On-Chip 802 Frame/s Multi-Layer Spiking Neural Network Learning. 1-3 - Sangdon Jung, Jehyeok Yu, Minsu Park, Jung-Hoon Chun:
A Crystal-Less Clock Generator for Low-Power and Low-Cost Sensor Transceivers with 12.9MHz-to-3.3GHz Range, 16.67ppm/°C Inaccuracy from -25°C to 85°C, and 0.25us Settle-Time. 1-3 - Xiangrong Huang, Haikun Jia, Wei Deng, Chuanming Zhu, Zhihua Wang, Xuzhi Liu, Zhiming Chen, Baoyong Chi:
A 4-Element 4-Beam Ka-Band Phased-Array Receiver Using Mesh Topology in 65 nm CMOS. 1-3 - Dong-Hyun Yoon, He Junsen, Kwang-Hyun Baek, Youngdon Choi, Jung-Hwan Choi, Tony Tae-Hyoung Kim:
A Time-Based PAM-4 Transceiver Using Single Path Decoder and Fast-Stochastic Calibration Techniques. 1-3 - Kent Edrian Lozada, Dong-Hun Lee, Ye-Dam Kim, Ho-Jin Kim, Youngjae Cho, Michael Choi, Seung-Tak Ryu:
A 25kHz-BW 97.4dB-SNDR 100.2dB-DR 3rd-Order SAR-Assisted CT DSM with 1-0 MASH and DNC. 1-3 - Huaiyu Liu, Yang Lin, Guoxing Wang, Yan Liu:
An $8.73\mathrm{G}\Omega$ Input Impedance VCO-Based Neural Front-End with Autonomous Time-Domain Impedance Boosting Technique and Maximum 0.215s Re-Calibration Time. 1-3 - Jiaming Zhang, Jiahao Lu, Dongsheng Liu, Aobo Li, Xiang Li, Shuo Yang, Ang Hu, Xuecheng Zou:
Flexible and Efficient Implementation of CRYSTALS-KYBER SIMD RISC-V Coprocessor Based on Customized Vector Instruction-Set Extension. 1-3 - Jonghang Choi, Subin Kim, Yongjun Lee, Sanghyun Heo, Keum-Dong Jung, Young-Ha Hwang, Jun-Eun Park:
A 1.08ms Ultrafast Scanning Capacitive Touch-Screen Sensor Interface with Charge-Interpolated Common-Mode Compensation and Host-Based Adaptive Median Filtering. 1-3 - Tzu-Wei Tong, Yi-Yen Hsieh, Tai-Jung Chen, Chia-Hsiang Yang:
A 73.8K Inference/mJ SVM Learning Accelerator for Brain Pattern Recognition. 1-3 - Timur Zirtiloglu, Peter Crary, Eyyup Tasci, Arslan Riaz, Yonina C. Eldar, Nir Shlezinger, Rabia Tugce Yazicigil:
Task-Specific Low-Power Beamforming MIMO Receiver Using 2-Bit Analog-to-Digital Converters. 1-3 - Sheng-Kai Chang, Shao-Ting Chang, Zhi-Wei Lin, Kuang-Wei Cheng:
An 890 μW Multichannel Injection-Locked OOK Transmitter with 23% Global Efficiency and 22 pJ/bit Energy Efficiency. 1-3 - Bongtae Kim:
5G Lessons Learned and an Outlook on 6G. 1-2 - Chan-Ho Kye, Kyojin Choo:
A 0.000261 mm2 Single-Channel 1 GS/s 8-Bit 3-Stage Capacitor Array-Assisted Charge-Injection DAC-Based SAR ADC in 28 nm CMOS. 1-3 - Yigi Kwon, Sangwoo Lee, Changuk Lee, Hyunchul Yoon, Byounghan Min, Youngcheol Chae:
An 11bit 360MS/s Pipelined SAR ADC with Dynamic Negative-C Assisted Residue Amplifier. 1-3 - Chao Xie, Guangshu Zhao, Junliang Wei, Man-Kay Law, Milin Zhang:
2-20-V Wide Input Range Active Rectifier with Single-Multiplexing Adaptive Delay Compensation and Low-Voltage Enhancement for Wireless Power Transmission. 1-3 - Chenyu Xu, Xiaofei Liao, Feifan Hong, Mengru Yang, Peijuan Ju, Wendi Chen, Pengfei Diao, Hao Gong, Xiang Liu, Xiaohu You, Dixian Zhao:
A 54-to-69-GHz Wideband 2T2R FMCW Radar Transceiver Employing Cascaded-PLL Topology and PTAT-Enhanced Temperature Compensation in 40-nm CMOS. 1-3 - Xin Zhang, Vishal Sharma, Yuncheng Lu, Yong-Jun Jo, Tony Tae-Hyoung Kim:
A 400MHz 249.1TOPS/W 64Kb Fully-Reconfigurable SRAM-Based Digital Compute-in-Memory Macro for Accelerating CNNs. 1-3 - Yubin Qin, Yang Wang, Dazheng Deng, Xiaolong Yang, Zhiren Zhao, Yang Zhou, Yuanqi Fan, Jingchuan Wei, Tianbao Chen, Leibo Liu, Shaojun Wei, Yang Hu, Shouyi Yin:
A 28nm 49.7TOPS/W Sparse Transformer Processor with Random-Projection-Based Speculation, Multi-Stationary Dataflow, and Redundant Partial Product Elimination. 1-3 - Wei Zhu, Jian Zhang, Jiazhi Ying, Xiangjie Yi, Yan Wang, Houjun Sun:
A Hybrid Integrated W-Band 4-Element Phased-Array Transceiver Front-End Achieving 21.6% Full TX Peak PAE at 14.8dBm Output Power and <1°/dB Phase/Gain Resolution in 65-nm CMOS Technology. 1-3 - Yuxuan Luo, Yutang Chen, Jianping Guo, Xian Tang, Dihu Chen:
An Instant-Setup On-Delay Compensation Scheme Based on Phase Detection for Series-Resonant Wireless Power Receiver with Up-to-4.41% Efficiency Enhancement. 1-3 - Mengru Yang, Chenyu Xu, Peng Gu, Yongran Yi, Mohan Guo, Liangliang Liu, Xiangxi Yan, Xiaohu You, Dixian Zhao:
K/Ka-Band 4-Element 4-Beam Hybrid Phased-Array Transmitter and Receiver Front-Ends with Compact Layout Floor-Plans and Fault-Tolerant Digital Circuits. 1-3 - Ruichang Ma, Haikun Jia, Hongzhuo Liu, Wei Deng, Zhihua Wang, Baoyong Chi:
IEEE ASSCC 2023/ Session 10/ Paper 10.5. 1-3 - Soyeon Um, Sangjin Kim, Seongyon Hong, Sangyeob Kim, Hoi-Jun Yoo:
LOG-CIM: A 116.4 TOPS/W Digital Computing-In-Memory Processor Supporting a Wide Range of Logarithmic Quantization with Zero-Aware 6T Dual-WL Cell. 1-3 - Yue Liang, Qin Chen, Xu Wu, Xiangning Fan, Lianming Li:
A 226 GHz Coupled Harmonic VCO with 9.34% Tuning Range Utilizing Three-Coil Transformer with Switched Inductor in 65nm CMOS. 1-3 - Bing-Jen Wu, Dao-Han Yao, Po-Hung Chen:
A 6.78-MHz Wireless Power Transfer System with Voltage-/Current-Mode 0X/1X Regulating Rectifier and Global-Loop Power Control. 1-3 - Daewon Rho, Jae-Koo Park, Seung-Jae Yang, Woo-Young Choi:
A 80Gb/s/pin Single-Ended PAM-4 Transmitter With an Edge Boosting Auxiliary Driver and a 4-Tap FFE in 28-nm CMOS. 1-3 - Hongzhi Liang, Yi Shen, Jun Chang, Shubin Liu, Ruixue Ding, Zhangming Zhu:
A 5GS/s 38.04dB SNDR Single-Channel TDC-Assisted Hybrid ADC with $\lambda/4$ Transmission Line Based Time Quantizer Achieving a PVT Robustness 416.6fs Time Step. 1-3 - Ken Takeuchi:
Foreword. 1-2 - Haoqi Qin, Junjie Gu, Hao Xu, Weitian Liu, Kefeng Han, Rui Yin, Zongming Duan, Hao Gao, Na Yan:
A 26-30GHz Digitally-Controlled Variable Gain Power Amplifier with Phase Compensation and Third Order Nonlinearity Cancellation Technique. 1-3 - Daeho Yun, Minsu Park, Kahyun Kim, Kyungmin Baek, Eonhui Lee, Woo-Seok Choi, Deog-Kyoon Jeong:
A PAM4 Level Mismatch Adjustment Scheme for 48-Gb/s PAM4 Memory Tester Bridge. 1-3 - Shutao Zhang, Malte Wabnitz, Tobias Gemmeke:
A Compact 1,257-Gbps/W Byte-Serial AES Accelerator for IoT Applications in 22 nm. 1-3 - Hanzhang Cao, Tongde Huang, Xiaolong Liu, Hao Wang, Jin Jin, Wen Wu:
A 5.2GHz Trifilar Transformer-Based Class-F23 Noise Circulating VCO with FoM of 192.6 dBc/Hz. 1-3 - Yoichi Iizuka, Akihide Maezono, Wataru Saito, Atsushi Yamane, Kazuhiko Takami, Fukashi Morishita:
A Low Noise 8Mpixel CMOS Image Sensor with 5.36GHz Global Counter and Dual Latch Skew Canceler for Surveillance AI Camera System. 1-3 - Rui Zhang, Dawei Tang, Zhe Chen, Liqun Lu, Peigen Zhou, Jixin Chen, Wei Hong:
A D-Band ASK Transmitter with 50GHz RF Bandwidth and Multi-Mode Interface Implemented in 28nm CMOS. 1-3 - Luigi Fassio, Hoang Hong Hanh, Massimo Alioto:
A Resistor/Trimming-Less Self-Biased Current Reference Class with Area Down to $3,500\ \mu \mathrm{m}^{2}$, 42.8 pW Power and 10.4% Accuracy across Corner Wafers in 180 nm. 1-3 - Peng Xu, Xueli Zhang, Tao Wang, Peng Cao, Jiawei Xu, Zhiliang Hong:
A 200MHz Bandwidth 84% Peak Efficiency AC-Coupled Envelope Tracking Supply Modulator with 10MHz Constant Switching Frequency. 1-3 - Yongjae Park, Jubin Kang, Dahwan Park, Insang Son, Jung-Hye Hwang, Seong-Jin Kim:
A $\mathbf{160}\times \mathbf{120}$ Indirect Time-of-Flight Sensor with Pixel-Level Adaptive $\Delta\Sigma$-Operations for Background Light Cancellation. 1-3 - Yoondeok Na, Seokho Yun, Myung-Jae Lee, Youngcheol Chae:
An 8.5ps Resolution, $2000\mu\mathrm{m}^{2}$ Phase-Domain Delta-Sigma TDC for Lidar Applications. 1-3 - Ziyi Lin, Haikun Jia, Chuanming Zhu, Wei Deng, Huabing Liao, Bao Shi, Lujie Hao, Xiangrong Huang, Baoyong Chi:
A 26.9-GHz 4-Element Code-Domain Hybrid Beamforming Phased-Array Receiver. 1-3 - Gokul Krishnan, Gopikrishnan Raveendran Nair, Jonghyun Oh, Anupreetham Anupreetham, Pragnya Sudershan Nalla, Ahmed Hassan, Injune Yeo, Kishore Kasichainula, Jae-sun Seo, Mingoo Seok, Yu Cao:
3D-ISC: A 65nm 3D Compatible In-Sensor Computing Accelerator with Reconfigurable Tile Architecture for Real-Time DVS Data Compression. 1-3 - Jian Zhang, Wei Zhu, Dawei Wang, Xiangjie Yi, Ruitao Wang, Yan Wang:
A Ka-Band Mutual Coupling Resilient Balanced PA with Magnetic Coupling Self-Cancelling Inductor Achieving 21.2dBm OP1dBand 27.6% PAE1dB. 1-3 - Hongzhi Wu, Weitao Wu, Liping Zhong, Xuxu Cheng, Xiongshi Luo, Zhenghao Li, Dongfan Xu, Quan Pan:
A 2 x 24Gb/s Single-Ended Transceiver with Channel-Independent Encoder-Based Crosstalk Cancellation in 28nm CMOS. 1-3 - Yanbo Zhang, Xianghui Zhang, Li Tian, Shubin Liu, Zhangming Zhu:
An 83.6dB-SNDR 101.6dB-SFDR 4th-Order Noise-Shaping SAR with 2nd-Order Nonlinearity Error Shaping. 1-3 - Debapriya Sahu, V. Srinivas, Rohit Chatterjee, Meghna Agarwal, P. Agrawal, R. Juluri, M. Mukherjee, Vimal Edayath, A. Yerramsetty, G. Bakalzuk, O. Rahmanony, K. Rajmohan, A Sancheti, R. Anand:
A Triple-Band Radio for WLAN 11b/g/n/ax in 45nm CMOS. 1-3 - Yixi Li, Zhao Zhang, Yong Chen, Xinyu Shen, Nan Qi, Jian Liu, Nanjian Wu, Liyuan Liu:
A 12.75-to-16-GHz Spur-Jitter-Joint-Optimization SS-PLL Achieving -94.55-dBc Reference Spur, 31.9-fs Integrated Jitter and -260.1-dB FoM. 1-3 - Seung Hun Choi, Jeongmin Kim, Jaewoong Ahn, Junyeol An, Jiwoong Kim, Ohjo Kwon, Ki-Duk Kim, Hyung-Min Lee:
An Area and Power Efficient Fully Nonlinear 10-bit Column Driver with Time-Shared Multi-Gamma-Slope DAC and Time-Interleaved Sampling Buffer for Mobile AMOLEDs. 1-3 - Hyeyeon Lee, Donguk Seo, Young-Jin Woo, Yoonmyung Lee, Inhee Lee, Youngcheol Chae:
A 23.9 µW 13.6-bit Period Modulation-Based Capacitance-to-Digital Converter with Dynamic Current Mirror Front-end Achieving Capacitor Range of 1 to 68 pF. 1-3 - Zizhao Ma, Xianwu Hu, Gan Wen, Yihao Wang, Zeming Wang, Yukai Lin, Yu Wang, Yuhao Guo, Yanlei Li, Xingdong Liang, Xiaoyang Zeng, Yufeng Xie:
GCFP-ACIM: A 40nm 4.74TFLOPS/W General Complex Float-Point Analog Compute-in-Memory with Adaptive Power-Saving for HDR Signal Processing Applications. 1-3 - Dongze Li, Wei Deng, Xintao Li, Ruiheng Qiu, Haikun Jia, Xiangrong Huang, Ziyuan Guo, Baoyong Chi:
A 27-to-31.6 GHz 8-Element Phased-Array Transmitter Front-End with Inter-Element-Interference Cancellation Scheme in 65 nm CMOS. 1-3 - Hyunji Kim, Eunkyung Ham, Sunyoung Park, Hana Kim, Ji-Hoon Kim:
A DRAM Bandwidth-Scalable Sparse Matrix-Vector Multiplication Accelerator with 89% Bandwidth Utilization Efficiency for Large Sparse Matrix. 1-3 - Yujie Geng, Haichuan Lin, Bo Wang, Cheng Wang:
A Cryo-CMOS 4.5~7GHz Dual-Qubit Homodyne Reflectometer Array with High Q Degenerate Parametric Amplifier Through Dynamic Mode Coupling. 1-2 - Jongjun Park, Donghyeon Han, Junha Ryu, Dongseok Im, Gwangtae Park, Hoi-Jun Yoo:
A 33.6 FPS Embedding based Real-time Neural Rendering Accelerator with Switchable Computation Skipping Architecture on Edge Device. 1-3 - Xiangao Qi, Yuqing Lou, Yongfu Li, Guoxing Wang, Kea-Tiong Tang, Jian Zhao:
A 5.37-TSOPS/W Reconfigurable Neuron Array with Dual-mode Neurons and Asynchronous Synapses for Energy-Efficient Inference and Biological Neural Network Simulation. 1-3 - Jiwon Choi, Sangyeob Kim, Wonhoon Park, Wooyoung Jo, Hoi-Jun Yoo:
A Resource-Efficient Super-Resolution FPGA Processor with Heterogeneous CNN and SNN Core Architecture. 1-3 - Changjoo Park, Jeongmyeong Kim, Kyounghun Kang, Minkyu Yang, Byeongmin Moon, Siheon Lee, Wanyeong Jung:
A 74.0 dB-SNDR 175.4 dB-FoM Pipelined-SAR ADC Using a Cyclically Charged Floating Inverter Amplifier. 1-3 - Yuxiao Zhao, Hanyang Wang, Yongming Xu, Zhongyuan Ying, Yu Lu, Jinlin Liu, Tuo Hu, Jin Mitsugi, Hao Min:
MSN: Battery-Less Multiple Subcarrier Multiple Access Sensor Node with Full-Duplex Backscatter Concurrent Data Streaming. 1-3 - Takeshi Yoshida, Shinsuke Hara, Tatsuo Hagino, Mohamed H. Mubarak, Akifumi Kasamatsu, Kyoya Takano, Yoshiki Sugimoto, Kunio Sakakibara, Shuhei Amakawa, Minoru Fujishima:
A 2D Beam-Steerable 252-285-GHz 25.8-Gbit/s CMOS Receiver Module. 1-3 - Liqun Feng, Qianxian Liao, Woogeun Rhee, Zhihua Wang:
A Low-Voltage Bias-Current-Free Pseudo-Differential Hybrid PLL Using a Time-Interleaving Flip-Flop Phase Detector. 1-3 - Toyohiro Shimogawa, Makoto Nonaka, Toma Ogata, Toshiki Kiryu, Yasuto Igarashi, Kosuke Yayama, Masahiro Kitamura, Hiromichi Ishikura, Mitsuru Hiraki, Masao Ito, Takashi Kono:
An On-Chip DC-DC Converter and Power Management System Achieving Zero Standby-to-Active Transition Time in MCU. 1-3 - Xiangdong Feng, Xin Liu, Yangfan Xuan, Fengheng Li, Yuxuan Luo, Ping Wang, Bo Zhao:
A 69μW Dual-Mode Electrochemical miR-21 Detection SoC with 3rd-Harmonic Direct-Solution Technique. 1-3 - Shinichi Ikeda, Akira Iwata, Goichi Otomo, Tomoaki Suzuki, Hiroaki Iijima, Mikio Shiraishi, Shinya Kawakami, Masatomo Eimitsu, Yoshiki Matsuoka, Kiyohito Sato, Shigehiro Tsuchiya, Yoshinori Shigeta, Takuma Aoyama:
A 6.4Gbps/pin NAND Flash Memory Multi-Chip Package Employing a Frequency Multiplying Bridge Chip for Scalable Performance and Capacity Storage Systems. 1-3 - I-Fan Lin, Yu-Chu Tsai, Heng-Li Lin, Yu-Te Liao:
An 18-nW, 170°C Temperature Range, Voltage and Current Reference Circuit with Low Line Sensitivity. 1-3 - Dawei Tang, Zekun Li, Leyang Huang, Rui Zhang, Liqun Lu, Chun Yang, Zheng Yan, Peigen Zhou, Zhe Chen, Jixin Chen, Wei Hong:
A 110-160 GHz ASK Receiver with Isomorphic Low Noise Power Amplifier and Multi-Mode Interface in 28-nm CMOS. 1-3 - Yutang Chen, Yuxuan Luo, Jianping Guo, Xian Tang, Dihu Chen:
A 2-W, 90%-Efficiency Single-Stage Dual-Output Wireless Power Receiver with 0.1 to 700-mA Output Current Range Through Dynamic Delay Compensation and Bootstrap Adaptive Body Biasing Circuit. 1-3 - Hyun-A. Ahn, Yoo-Chang Sung, Yong-Hun Kim, Janghoo Kim, Kihan Kim, Donghun Lee, Young-Gil Go, Jae-Woo Lee, Jae-Woo Jung, Yong-Hyun Kim, Garam Choi, Jun-Seo Park, Bo-Hyeon Lee, Jin-Hyeok Baek, Daesik Moon, Daihyun Lim, Seung-Jun Bae, Young-Soo Sohn, Changsik Yoo, Tae-Young Oh:
A 1.01V 8.5Gb/s/pin 16Gb LPDDR5x SDRAM with Self-Pre-Emphasized Stacked-Tx, Supply Voltage Insensitive Rx, and Optimized Clock Using 4th-Generation 10nm DRAM Process for High-Speed and Low-Power Applications. 1-4 - Cong Wei, Rongshan Wei, Lijie Huang, Gongxing Huang, Jinze Lai, Zhichao Tan:
A 1.2 V 2.3 µW 94.7 dB DR Delta-Sigma Modulator With Dynamic-Range Enhancement and Tri-Level CDAC. 1-3 - Masayuki Ito:
Architecture Challenges for Heterogeneous Processors in Embedded SoCs. 1-2 - Yuke Shen, Shubin Liu, Kui Wen, Yanbo Zhang, Yi Shen, Ruixue Ding, Zhangming Zhu:
A $142.8-\mu \text{W}$ 98.1dB-SNDR Power/Bandwidth Configurable Fully Dynamic Discrete-Time Zoom ADC with Interstage Leakage Shaping. 1-3 - Zhengguo Shen, Junyi Qian, Keran Li, Ziyu Li, Lishuo Deng, Weiwei Shan:
TEPD: A Compound Timing Detection of Both Data-Transition and Path-Activation for Reliable In-Situ Timing Error Detection and Correction in 28nm CMOS. 1-3 - Gengzhen Qi, Pui-In Mak:
A 0.5-to-1.5GHz BW-Extended Gain-Boosted N-Path Filter Using a Switched $\mathbf{g}_{\mathbf{m}}-\mathbf{C}$ Network Achieving 50MHz BW and 18.2dBm OB-IIP3. 1-3 - Jinook Jung, Jun-Han Choi, Kyoung-Jun Roh, Jaewoo Park, Won-Mook Lim, Tae-Sung Kim, Han-Ki Jeong, Myoungbo Kwak, Jaeyoun Youn, Jeong-Don Ihm, Changsik Yoo, Youngdon Choi, Jung-Hwan Choi, Hyungjong Ko:
A 4ns Settling Time FVF-Based Fast LDO Using Bandwidth Extension Techniques for HBM3. 1-3 - Kyungmin Lee, Jaehong Jung, Gyusik Kim, Joomyoung Kim, Seungjin Kim, Seunghyun Oh, Sung Min Park, Jongwoo Lee:
A Wide Frequency Range, Small Area and Low Supply Memory Interface PLL Using a Process and Temperature Variation Aware Current Reference in 3 nm Gate-All Around CMOS. 1-3
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