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2020 – today
- 2024
[j2]Dong-Hun Lee
, Kent Edrian Lozada, Ye-Dam Kim, Ho-Jin Kim, Youngjae Cho, Michael Choi, Seung-Tak Ryu:
A 25-kHz-BW 97.4-dB-SNDR SAR-Assisted Continuous-Time 1-0 MASH Delta-Sigma Modulator With Digital Noise Coupling. IEEE J. Solid State Circuits 59(10): 3232-3241 (2024)- [j1]Jihun Choi, Sangwook Na, Hojin Kim, Hyungdong Roh, Youngjae Cho, Michael Choi, Min-Seong Choo, Jeongjin Roh:
High-Precision Built-In Phase Noise Measurement Circuit With a Hybrid ΔΣ Time-to-Digital Converter for SoC Clocking Applications. IEEE Trans. Circuits Syst. II Express Briefs 71(11): 4613-4617 (2024) - [c11]Youngjae Cho, HeeSun Bae, Seungjae Shin, Yeo Dong Youn, Weonyoung Joo, Il-Chul Moon:
Make Prompts Adaptable: Bayesian Modeling for Vision-Language Prompt Learning with Data-Dependent Prior. AAAI 2024: 11552-11560 - [c10]Sangheon Lee, Jinwoo Park, Junsang Park, Sangkyu Lee, Jungho Lee, Youngjae Cho, Michael Choi, Jongshin Shin:
3.9 A 1.2V High-Voltage-Tolerant Bootstrapped Analog Sampler in 12-bit SAR ADC Using 3nm GAA's 0.7V Thin-Gate-Oxide Transistor. ISSCC 2024: 70-72 - [c9]Byeongwoo Koo, Sunghan Do, Sangkyu Lee, Sang-Pil Nam, Heewook Shin, Saemin Im, Hyochul Shin, Sungno Lee, Junsang Park, Jungho Lee, Youngjae Cho, Michael Choi, Jongshin Shin:
A 12-bit 16GS/s Single-Channel RF-DAC with Hybrid Segmentation for Digital Back-Off and Code-Dependent Free Switch Driver Achieving -85dBc IMD3 in 5nm FinFET. VLSI Technology and Circuits 2024: 1-2 - [c8]Kent Edrian Lozada, Ye-Dam Kim, Ho-Jin Kim, Youngjae Cho, Michael Choi, Seung-Tak Ryu:
A 0.38mW 200kHz-BW 92.1dB-DR Single-Opamp 4th-Order Continuous-Time Delta-Sigma Modulator with 3rd-Order Noise Coupling. VLSI Technology and Circuits 2024: 1-2 - [c7]Junsang Park, Jinwoo Park, Jaemin Hong, Sun-Jae Park, Dongsuk Lee, Sungno Lee, Hyochul Shin, Kyung-Hoon Lee, Byeongwoo Koo, Youngjae Cho, Michael Choi, Jongshin Shin:
A 12-bit 10GS/s Time-Interleaved SAR ADC with Even/Odd Channel-Correlated Absolute Error-Based Over-Nyquist Timing-Skew Calibration in 5nm FinFET. VLSI Technology and Circuits 2024: 1-2 - [i2]Youngjae Cho, HeeSun Bae, Seungjae Shin, Yeo Dong Youn, Weonyoung Joo, Il-Chul Moon:
Make Prompts Adaptable: Bayesian Modeling for Vision-Language Prompt Learning with Data-Dependent Prior. CoRR abs/2401.06799 (2024) - [i1]Youngjae Cho, Gwangyeol Kim, Sirojbek Safarov, Seongdeok Bang, Jaewoo Park:
Revisiting DDIM Inversion for Controlling Defect Generation by Disentangling the Background. CoRR abs/2411.16767 (2024) - 2023
- [c6]Kent Edrian Lozada, Dong-Hun Lee, Ye-Dam Kim, Ho-Jin Kim, Youngjae Cho, Michael Choi, Seung-Tak Ryu:
A 25kHz-BW 97.4dB-SNDR 100.2dB-DR 3rd-Order SAR-Assisted CT DSM with 1-0 MASH and DNC. A-SSCC 2023: 1-3 - [c5]Yoon-Yeong Kim, Youngjae Cho, JoonHo Jang, Byeonghu Na, Yeongmin Kim, Kyungwoo Song, Wanmo Kang, Il-Chul Moon:
SAAL: Sharpness-Aware Active Learning. ICML 2023: 16424-16440 - 2022
- [c4]Byeongwoo Koo, Sunghan Do, Sang-Pil Nam, Heewook Shin, Sungno Lee, Eunhye Oh, Jaemin Hong, Jung-Ho Lee, Youngjae Cho, Michael Choi, Jongshin Shin:
A 12-bit 8GS/s RF Sampling DAC with Code-Dependent Nonlinearity Compensation and Intersegmental Current-Mismatch Calibration in 5nm FinFET. VLSI Technology and Circuits 2022: 86-87 - [c3]Kyung-Hoon Lee, Jinwoo Park, Younghyo Park, Byeongwoo Koo, Sunghan Do, Woongtaek Lim, Sungno Lee, Hyochul Shin, Eunhye Oh, Youngjae Cho, Michael Choi, Jongshin Shin:
An Automotive ASIL-D Safety Mechanism in ADC and DAC for Communication Application. VLSI Technology and Circuits 2022: 142-143 - 2021
- [c2]Seung-Yeob Baek, Il-Hoon Jang, Michael Choi, Hyungdong Roh, Woongtaek Lim, Youngjae Cho, Jongshin Shin:
A 12b 600MS/s Pipelined SAR and 2x-Interleaved Incremental Delta-Sigma ADC with Source-Follower-Based Residue-Transfer Scheme in 7nm FinFET. ISSCC 2021: 172-174 - [c1]Yeongmin Kim, Youngjae Cho, Hanbit Lee, Il-Chul Moon:
Predict Sequential Credit Card Delinquency with VaDE-Seq2Seq. SMC 2021: 1159-1164
Coauthor Index
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