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2020 – today
- 2023
[c12]Atif Yasin, Tiankai Su, Sébastien Pillement, Maciej J. Ciesielski:
Formal Verification of Divider Circuits by Hardware Reduction. SMACD 2023: 1-4- 2022
- [c11]Maciej J. Ciesielski, Atif Yasin, Jiteshri Dasari:
Functional Verification of Arithmetic Circuits: Survey of Formal Methods. DDECS 2022: 94-99 - 2020
- [j2]Maciej J. Ciesielski
, Tiankai Su, Atif Yasin, Cunxi Yu:
Understanding Algebraic Rewriting for Arithmetic Circuit Verification: A Bit-Flow Model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(6): 1346-1357 (2020) - [c10]Atif Yasin, Tiankai Su, Sébastien Pillement, Maciej J. Ciesielski:
SPEAR: Hardware-based Implicit Rewriting for Square-root Circuit Verification. DATE 2020: 532-537 - [c9]Dinesh D. Narasimharaju, R. S. Suraj Rao, Akshaya Sandeep Waingade, Atif Yasin, Maciej J. Ciesielski:
Dual Approach to Solving SAT in Hardware. DTIS 2020: 1-6 - [c8]Tiankai Su, Atif Yasin, Sébastien Pillement, Maciej J. Ciesielski:
Formal Verification of Constrained Arithmetic Circuits using Computer Algebraic Approach. ISVLSI 2020: 386-391
2010 – 2019
- 2019
- [j1]Rubia Fatima, Affan Yasin, Lin Liu, Jianmin Wang, Wasif Afzal, Atif Yasin:
Improving software requirements reasoning by novices: a story-based approach. IET Softw. 13(6): 564-574 (2019) - [c7]Cunxi Yu, Tiankai Su, Atif Yasin, Maciej J. Ciesielski:
Spectral approach to verifying non-linear arithmetic circuits. ASP-DAC 2019: 261-267 - [c6]Atif Yasin, Tiankai Su, Sébastien Pillement, Maciej J. Ciesielski:
Formal Verification of Integer Dividers: Division by a Constant. ISVLSI 2019: 76-81 - [c5]Atif Yasin, Tiankai Su, Sébastien Pillement, Maciej J. Ciesielski:
Functional Verification of Hardware Dividers using Algebraic Model. VLSI-SoC 2019: 257-262 - [i1]Cunxi Yu, Tiankai Su, Atif Yasin, Maciej J. Ciesielski:
Spectral Approach to Verifying Non-linear Arithmetic Circuits. CoRR abs/1901.02950 (2019) - 2018
- [c4]Tiankai Su, Atif Yasin, Cunxi Yu, Maciej J. Ciesielski:
Computer Algebraic Approach to Verification and Debugging of Galois Field Multipliers. ISCAS 2018: 1-5 - [c3]Cunxi Yu, Atif Yasin, Tiankai Su, Alan Mishchenko, Maciej J. Ciesielski:
Rewriting Environment for Arithmetic Circuit Verification. LPAR 2018: 656-666 - 2017
- [c2]Tiankai Su, Cunxi Yu, Atif Yasin, Maciej J. Ciesielski:
Formal Verification of Truncated Multipliers Using Algebraic Approach and Re-Synthesis. ISVLSI 2017: 415-420 - 2016
- [c1]Atif Yasin, Jeff Jun Zhang, Hu Chen, Siddharth Garg, Sanghamitra Roy, Koushik Chakraborty:
Synergistic timing speculation for multi-threaded programs. DAC 2016: 51:1-51:6
Coauthor Index
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