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ORCIDJens Peter Wittenburg
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2000 – 2009
- 2008
[c6]Thomas Brune, Axel Kochale, Jens Peter Wittenburg:
IT leverage for media acquisition: New paradigms in the key area of digital cinematography and HD production workflows. ICME 2008: 1601-1602- 2004
- [b1]Jens Peter Wittenburg:
Ein Beitrag zur Design-Raum-Evaluierung von SMT-Architekturen für objektbasierte Multimedia-Anwendungen. University of Hanover, 2004, ISBN 3-18-374110-5, pp. 1-158 - [c5]Jens Peter Wittenburg, Ulrich Schreiber, Ulrich Gries, Markus Schneider, Tim Niggemeier:
A Cost-Efficient RISC Processor Platform for Real Time Audio Applications. SAMOS 2004: 39-48 - 2002
- [c4]Helge Kloos, Jens Peter Wittenburg, Willm Hinrichs, Hanno Lieske, Lars Friebe, C. Klar, Peter Pirsch:
HiPAR-DSP 16, a scalable highly parallel DSP core for system on a chip video- and image processing applications. ICASSP 2002: 3112-3115 - [c3]Peter Pirsch, Achim Freimann, C. Klar, Jens Peter Wittenburg:
Processor Architectures for Multimedia Applications. Embedded Processor Design Challenges 2002: 188-206 - 2001
- [j3]Peter Pirsch, Carsten Reuter, Jens Peter Wittenburg, Mark Bernd Kulaczewski, Hans-Joachim Stolberg:
Architecture Concepts for Multimedia Signal Processing. J. VLSI Signal Process. 29(3): 157-165 (2001) - 2000
- [j2]Willm Hinrichs, Jens Peter Wittenburg, Hanno Lieske, Helge Kloos, Martin Ohmacht
, Peter Pirsch:
A 1.3-GOPS parallel DSP for high-performance image-processing applications. IEEE J. Solid State Circuits 35(7): 946-952 (2000)
1990 – 1999
- 1999
- [c2]Jens Peter Wittenburg, Willm Hinrichs, Martin Ohmacht, Hanno Lieske, Helge Kloos, Peter Pirsch:
HiPAR-DSP: Ein 1.3 GOPS Multimedia Signalprozessor. ARCS 1999: 15-21 - 1998
- [c1]Jens Peter Wittenburg, Willm Hinrichs, Johannes Kneip, Martin Ohmacht, Mladen Berekovic, Hanno Lieske, Helge Kloos, Peter Pirsch:
Realization of a Programmable Parallel DSP for High Performance Image Processing Applications. DAC 1998: 56-61 - 1997
- [j1]Johannes Kneip, Mladen Berekovic, Jens Peter Wittenburg, Willm Hinrichs, Peter Pirsch:
An Algorithm Adapted Autonomous Controlling Concept for a Parallel Single-Chip Digital Signal Processor. J. VLSI Signal Process. 16(1): 31-40 (1997)
Coauthor Index
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