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ORCIDElisardo Antelo
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2010 – 2019
- 2019
[c20]Álvaro Vázquez, Elisardo Antelo:
New 3D Projection Transformation for Point Clouds. ARITH 2019: 77-83- [i1]Elisardo Antelo:
ENBB Processor: Towards the ExaScale Numerical Brain Box [Position Paper]. CoRR abs/1902.06655 (2019) - 2017
- [j25]Elisardo Antelo
, Paolo Montuschi, Alberto Nannarelli:
Improved 64-bit Radix-16 Booth Multiplier Based on Partial Product Array Height Reduction. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(2): 409-418 (2017) - [c19]Álvaro Vázquez, Elisardo Antelo:
A Number System Approach for Adder Topologies. ARITH 2017: 50-57 - [c18]Álvaro Vázquez, Elisardo Antelo:
A Sum Error Detection Scheme for Decimal Arithmetic. ARITH 2017: 172-179 - 2016
- [j24]Lois Orosa, Javier D. Bruguera, Elisardo Antelo:
Asymmetric Allocation in a Shared Flexible Signature Module for Multicore Processors. Comput. J. 59(10): 1453-1469 (2016) - 2014
- [j23]Álvaro Vázquez, Elisardo Antelo, Javier D. Bruguera:
Fast Radix-10 Multiplication Using Redundant BCD Codes. IEEE Trans. Computers 63(8): 1902-1914 (2014) - 2012
- [j22]Lois Orosa, Elisardo Antelo, Javier D. Bruguera:
FlexSig: Implementing flexible hardware signatures. ACM Trans. Archit. Code Optim. 8(4): 30:1-30:20 (2012) - [j21]Elisardo Antelo, David Hough, Paolo Ienne:
Guest Editors' Introduction: Special Section on Computer Arithmetic. IEEE Trans. Computers 61(8): 1057-1058 (2012) - [j20]Álvaro Vázquez, Julio Villalba-Moreno, Elisardo Antelo, Emilio L. Zapata:
Redundant Floating-Point Decimal CORDIC Algorithm. IEEE Trans. Computers 61(11): 1551-1562 (2012) - 2011
- [j19]Fabrizio Lamberti, Nikolaos Andrikos, Elisardo Antelo, Paolo Montuschi:
Reducing the Computation Time in (Short Bit-Width) Two's Complement Multipliers. IEEE Trans. Computers 60(2): 148-156 (2011) - [e1]Elisardo Antelo, David Hough, Paolo Ienne:
20th IEEE Symposium on Computer Arithmetic, ARITH 2011, Tübingen, Germany, 25-27 July 2011. IEEE Computer Society 2011, ISBN 978-0-7695-4318-5 [contents] - 2010
- [j18]Álvaro Vázquez, Elisardo Antelo, Paolo Montuschi:
Improved Design of High-Performance Parallel Decimal Multipliers. IEEE Trans. Computers 59(5): 679-693 (2010)
2000 – 2009
- 2009
- [j17]Elisardo Antelo:
A Comment on "Beyond Fat-tree: Unidirectional Load-Balanced Multistage Interconnection Network". IEEE Comput. Archit. Lett. 8(1): 33-34 (2009) - [c17]Álvaro Vázquez, Elisardo Antelo:
A High-Performance Significand BCD Adder with IEEE 754-2008 Decimal Rounding. IEEE Symposium on Computer Arithmetic 2009: 135-144 - [c16]Álvaro Vázquez, Julio Villalba, Elisardo Antelo:
Computation of Decimal Transcendental Functions Using the CORDIC Algorithm. IEEE Symposium on Computer Arithmetic 2009: 179-186 - 2008
- [j16]Elisardo Antelo, Julio Villalba, Emilio L. Zapata:
A Low-Latency Pipelined 2D and 3D CORDIC Processors. IEEE Trans. Computers 57(3): 404-417 (2008) - [c15]Álvaro Vázquez, Elisardo Antelo:
New insights on Ling adders. ASAP 2008: 227-232 - 2007
- [c14]Álvaro Vázquez, Elisardo Antelo, Paolo Montuschi:
A New Family of High.Performance Parallel Decimal Multipliers. IEEE Symposium on Computer Arithmetic 2007: 195-204 - [c13]Álvaro Vázquez, Elisardo Antelo, Paolo Montuschi:
A radix-10 SRT divider based on alternative BCD codings. ICCD 2007: 280-287 - 2005
- [j15]Tomás Lang, Elisardo Antelo:
High-Throughput CORDIC-Based Geometry Operations for 3D Computer Graphics. IEEE Trans. Computers 54(3): 347-361 (2005) - [j14]Elisardo Antelo, Tomás Lang, Paolo Montuschi, Alberto Nannarelli:
Digit-Recurrence Dividers with Reduced Logical Depth. IEEE Trans. Computers 54(7): 837-851 (2005) - [c12]Elisardo Antelo, Tomás Lang, Paolo Montuschi, Alberto Nannarelli:
Low Latency Digit-Recurrence Reciprocal and Square-Root Reciprocal Algorithm and Architecture. IEEE Symposium on Computer Arithmetic 2005: 147-154 - [c11]Elisardo Antelo, Julio Villalba:
Low Latency Pipelined Circular CORDIC. IEEE Symposium on Computer Arithmetic 2005: 280-287 - 2003
- [j13]Tomás Lang, Elisardo Antelo:
Radix-4 Reciprocal Square-Root and Its Combination with Division and Square Root. IEEE Trans. Computers 52(9): 1100-1114 (2003) - [j12]Álvaro Vázquez, Elisardo Antelo:
Implementation of the Exponential Function in a Floating-Point Unit. J. VLSI Signal Process. 33(1-2): 125-145 (2003) - 2002
- [c10]Elisardo Antelo, Tomás Lang, Paolo Montuschi, Alberto Nannarelli:
Fast Radix-4 Retimed Division with Selection by Comparisons. ASAP 2002: 185-196 - 2001
- [c9]Tomás Lang, Elisardo Antelo:
Correctly Rounded Reciprocal Square-Root by Digit Recurrence and Radix-4 Implementation. IEEE Symposium on Computer Arithmetic 2001: 83-93 - 2000
- [j11]Elisardo Antelo, Tomás Lang, Javier D. Bruguera:
Very-High Radix Circular CORDIC: Vectoring and Unified Rotation/Vectoring. IEEE Trans. Computers 49(7): 727-739 (2000) - [j10]Tomás Lang, Elisardo Antelo:
CORDIC-Based Computation of ArcCos. J. VLSI Signal Process. 25(1): 19-38 (2000) - [j9]Elisardo Antelo, Tomás Lang, Javier D. Bruguera:
Very-High Radix CORDIC Rotation Based on Selection by Rounding. J. VLSI Signal Process. 25(2): 141-153 (2000)
1990 – 1999
- 1999
- [c8]Elisardo Antelo, Tomás Lang, Javier D. Bruguera:
Very-High Radix CORDIC Vectoring with Scalings and Selection by Rounding. IEEE Symposium on Computer Arithmetic 1999: 204- - 1998
- [j8]Elisardo Antelo, Tomás Lang, Javier D. Bruguera:
Computation of sqrt(x/d) in a Very High Radix Combined Division/Square-Root Unit with Scaling. IEEE Trans. Computers 47(2): 152-161 (1998) - [j7]Tomás Lang, Elisardo Antelo:
CORDIC Vectoring with Arbitrary Target Value. IEEE Trans. Computers 47(7): 736-749 (1998) - [j6]Elisardo Antelo, Montserrat Bóo, Javier D. Bruguera, Emilio L. Zapata:
A novel design of a two operand normalization circuit. IEEE Trans. Very Large Scale Integr. Syst. 6(1): 173-176 (1998) - [j5]Julio Villalba, Emilio L. Zapata, Elisardo Antelo, Javier D. Bruguera:
Radix-4 Vectoring CORDIC Algorithm and Architectures. J. VLSI Signal Process. 19(2): 127-147 (1998) - 1997
- [j4]Elisardo Antelo, Julio Villalba, Javier D. Bruguera, Emilio L. Zapata:
High Performance Rotation Architectures Based on the Radix-4 CORDIC Algorithm. IEEE Trans. Computers 46(8): 855-870 (1997) - [j3]Elisardo Antelo, Javier D. Bruguera, Tomás Lang, Emilio L. Zapata:
Error Analysis and Reduction for Angle Calculation Using the CORDIC Algorithm. IEEE Trans. Computers 46(11): 1264-1271 (1997) - [c7]Tomás Lang, Elisardo Antelo:
CORDIC Vectoring with Arbitrary Target Value. IEEE Symposium on Computer Arithmetic 1997: 108-115 - [c6]Tomás Lang, Elisardo Antelo:
CORDIC-based computation of arccos and arcsin. ASAP 1997: 132-143 - 1996
- [j2]Elisardo Antelo, Javier D. Bruguera, Emilio L. Zapata:
Unified Mixed Radix 2-4 Redundant CORDIC Processor. IEEE Trans. Computers 45(9): 1068-1073 (1996) - [c5]Julio Villalba, J. C. Arrabal, Emilio L. Zapata, Elisardo Antelo, Javier D. Bruguera:
Radix-4 Vectoring Cordic Algorithm And Architectures. ASAP 1996: 55-64 - [c4]Elisardo Antelo, Javier D. Bruguera, Tomás Lang, Julio Villalba, Emilio L. Zapata:
High Radix Cordic Rotation Based on Selection by Rounding. Euro-Par, Vol. II 1996: 155-164 - 1995
- [c3]Elisardo Antelo, Javier D. Bruguera, Julio Villalba, Emilio L. Zapata:
Redundant CORDIC Rotator Based on Parallel Prediction. IEEE Symposium on Computer Arithmetic 1995: 172-179 - [c2]Roberto R. Osorio, Elisardo Antelo, Javier D. Bruguera, Julio Villalba, Emilio L. Zapata:
Digit On-line Large Radix CORDIC Rotator. ASAP 1995: 246-257 - [c1]Julio Villalba, José Antonio Hidalgo López, Emilio L. Zapata, Elisardo Antelo, Javier D. Bruguera:
CORDIC Architectures with Parallel Compensation of the Scale Factor. ASAP 1995: 258-269 - 1993
- [j1]Javier D. Bruguera, Elisardo Antelo, Emilio L. Zapata:
Design of a Pipelined Radix 4 CORDIC Processor. Parallel Comput. 19(7): 729-744 (1993)
Coauthor Index
aka: Julio Villalba-Moreno
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