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2000 – 2009
- 2005
[c45]Eduard Cerny, Ashvin Dsouza, Kevin Harer, Pei-Hsin Ho, Hi-Keung Tony Ma:
Supporting sequential assumptions in hybrid verification. ASP-DAC 2005: 1035-1038- 2004
- [j35]Ying Xu, Xiaoyu Song, Eduard Cerny, Otmane Aït Mohamed:
Model Checking for a First-Order Temporal Logic Using Multiway Decision Graphs (MDGs). Comput. J. 47(1): 71-84 (2004) - [j34]Otmane Aït Mohamed, Xiaoyu Song, Eduard Cerny, Sofiène Tahar, Zijian Zhou:
MDG-Based State Enumeration By Retiming And Circuit Transformation. J. Circuits Syst. Comput. 13(5): 1111-1132 (2004) - 2003
- [j33]Otmane Aït Mohamed, Xiaoyu Song, Eduard Cerny:
On the non-termination of M-based abstract state enumeration. Theor. Comput. Sci. 300(1-3): 161-179 (2003) - 2002
- [c44]Yi Feng, Eduard Cerny:
Term ordering problem on MDG. ACM Great Lakes Symposium on VLSI 2002: 160-165 - [c43]Yi Feng, Eduard Cerny:
Variable ordering on multiway decision graphs. ISCAS (5) 2002: 337-340 - 2000
- [c42]Jin Hou, Eduard Cerny:
Model Reductions and a Case Study. FMCAD 2000: 299-315 - [c41]M. S. Jahanpour, Eduard Cerny:
Compositional verification of an ATM switch module using interface recognizer/suppliers (IRS). HLDVT 2000: 71-76
1990 – 1999
- 1999
- [j32]Abdessatar Abderrahman, Eduard Cerny, Bozena Kaminska:
Worst case tolerance analysis and CLP-based multifrequency test generation for analog circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(3): 332-345 (1999) - [j31]Sofiène Tahar, Xiaoyu Song, Eduard Cerny, Zijian Zhou, Michel Langevin, Otmane Aït Mohamed:
Modeling and formal verification of the Fairisle ATM switch fabricusing MDGs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(7): 956-972 (1999) - [j30]Samir Boubezari, Eduard Cerny, Bozena Kaminska, Benoit Nadeau-Dostie:
Testability analysis and test-point insertion in RTL VHDL specifications for scan-based BIST. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(9): 1327-1340 (1999) - [c40]Ying Xu, Eduard Cerny, Allan Silburt, A. Coady, Ying Liu, Philip Pownall:
Practical Application of Formal Verification Techniques on a Frame Mux/Demux Chip from Nortel Semiconductors. CHARME 1999: 110-124 - [c39]Eduard Cerny, Fen Jin:
Verification of Real Time Controllers Against Timing Diagram Specifications Using Constraint Logic Programming. ICCD 1999: 32-39 - [c38]E. K. Ogoubi, Eduard Cerny:
Synthesis of checker EFSMs from timing diagram specifications. ISCAS (1) 1999: 13-18 - [c37]Sophie Renault, Eduard Cerny:
Improving Termination of MDG-Based Abstract State Enumeration via Term Schematization. SMC@FLoC 1999: 57-74 - 1998
- [j29]Karim Khordoc, Eduard Cerny:
Semantics and verification of action diagrams with linear timing. ACM Trans. Design Autom. Electr. Syst. 3(1): 21-50 (1998) - [c36]Ying Xu, Eduard Cerny, Xiaoyu Song, Francisco Corella, Otmane Aït Mohamed:
Model Checking for a First-Order Temporal Logic Using Multiway Decision Graphs. CAV 1998: 219-231 - [c35]Abdelhalim El-Aboudi, El Mostapha Aboulhamid, Eduard Cerny:
Synthesis of interface controllers from timing diagram specifications. CICC 1998: 89-92 - [c34]Maroun Kassab, Eduard Cerny, Sidi Aourid, Thomas H. Krodel:
Propagation of Last-Transition-Time Constraints in Gate-Level Timing Analysis. DATE 1998: 796-802 - [c33]Eduard Cerny, Fen Jin:
Verification of Real Time Controllers Against Timing Diagram Specifications Using Constraint Logic Programming. EUROMICRO 1998: 10229-10236 - [c32]Fen Jin, Henrik Hulgaard, Eduard Cerny:
Maximum Time Separation of Events in Cyclic Systems with Linear and Latest Timing Constraints. FMCAD 1998: 167-184 - [c31]Otmane Aït Mohamed, Eduard Cerny, Xiaoyu Song:
MDG-based Verification by Retiming and Combinational Transformations. Great Lakes Symposium on VLSI 1998: 356-361 - 1997
- [j28]Francisco Corella, Zijian Zhou, Xiaoyu Song, Michel Langevin, Eduard Cerny:
Multiway Decision Graphs for Automated Hardware Verification. Formal Methods Syst. Des. 10(1): 7-46 (1997) - [j27]Jocelyn Cloutier, Eduard Cerny, F. Guertin:
Model partitioning and the performance of distributed timewarp simulation of logic circuits. Simul. Pract. Theory 5(1): 83-99 (1997) - [j26]Pierre Girodias, Eduard Cerny, William J. Older:
Solving Linear, Min and Max Constraint Systems Using CLP Based on Relational Interval Arithmetic. Theor. Comput. Sci. 173(1): 253-281 (1997) - [c30]Otmane Aït Mohamed, Xiaoyu Song, Eduard Cerny:
On the non-termination of MDGs-based abstract state enumeration. CHARME 1997: 218-235 - [c29]Pierre Girodias, Eduard Cerny:
Interface timing verification with delay correlation using constraint logic programming. ED&TC 1997: 12-19 - [c28]Eduard Cerny, Francisco Corella, Michel Langevin, Xiaoyu Song, Sofiène Tahar, Zijian Zhou:
Verification with Abstract State Machines Using MDGs. Formal Hardware Verification 1997: 79-113 - [c27]Abdessatar Abderrahman, Eduard Cerny, Bozena Kaminska:
CLP-based Multifrequency Test Generation for Analog Circuits. VTS 1997: 158-165 - 1996
- [j25]Abdessatar Abderrahman, Bozena Kaminska, Eduard Cerny:
Optimization-based multifrequency test generation for analog circuits. J. Electron. Test. 9(1-2): 59-73 (1996) - [j24]Guy Bois, Eduard Cerny:
Efficient generation of diagonal constraints for 2-D mask compaction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(9): 1119-1126 (1996) - [j23]Michel Langevin, Eduard Cerny:
A recursive technique for computing lower-bound performance of schedules. ACM Trans. Design Autom. Electr. Syst. 1(4): 443-455 (1996) - [c26]K. D. Anon, N. Boulerice, Eduard Cerny, Francisco Corella, Michel Langevin, Xiaoyu Song, Sofiène Tahar, Ying Xu, Zijian Zhou:
MDG Tools for the Verification of RTL Designs. CAV 1996: 433-436 - [c25]Jindrich Zejda, Eduard Cerny, S. Shenoy, Nicholas C. Rumin:
Bounding Switching Activity in CMOS Circuits Using Constraint Resolution. ED&TC 1996: 294-301 - [c24]Zijian Zhou, Xiaoyu Song, Sofiène Tahar, Eduard Cerny, Francisco Corella, Michel Langevin:
Formal Verification of the Island Tunnel Controller Using Multiway Decision Graphs. FMCAD 1996: 233-247 - [c23]Sofiène Tahar, Zijian Zhou, Xiaoyu Song, Eduard Cerny, Michel Langevin:
Formal Verification of an ATM Switch Fabric using Multiway Decision Graphs. Great Lakes Symposium on VLSI 1996: 106-111 - [c22]Michel Langevin, Sofiène Tahar, Zijian Zhou, Xiaoyu Song, Eduard Cerny:
Behavioral Verification of an ATM Switch Fabric using Implicit Abstract State Enumeration. ICCD 1996: 20-26 - 1995
- [c21]Francisco Corella, Michel Langevin, Eduard Cerny, Zijian Zhou, Xiaoyu Song:
State enumeration with abstract descriptions of state machines. CHARME 1995: 146-160 - [c20]Pierre Girodias, Eduard Cerny, William J. Older:
Solving Linear, Min and Max Constraint Systems Using CLP based on Relational Interval Arithmetic. CP 1995: 186-203 - [c19]Zijian Zhou, Xiaoyu Song, Francisco Corella, Eduard Cerny, Michel Langevin:
Partitioning transition relations efficiently and automatically. Great Lakes Symposium on VLSI 1995: 106-111 - 1994
- [j22]Younès Karkouri, El Mostapha Aboulhamid, Eduard Cerny, Alain Verreault:
Use of Fault Dropping for Multiple Fault Analysis. IEEE Trans. Computers 43(1): 98-103 (1994) - [j21]Jianli Sun, Eduard Cerny, Jan Gecsei:
Fault Tolerance in a Class of Sorting Networks. IEEE Trans. Computers 43(7): 827-837 (1994) - [c18]Michel Langevin, Eduard Cerny, Jörg Wilberg, Heinrich Theodor Vierhaus:
Local microcode generation in system design. Code Generation for Embedded Processors 1994: 171-187 - [c17]Michel Langevin, Eduard Cerny:
An Extended OBDD Representation for Extended FSMs. EDAC-ETC-EUROASIC 1994: 208-213 - [c16]Jindrich Zejda, Eduard Cerny:
Gate-level timing verification using waveform narrowing. EURO-DAC 1994: 374-379 - [c15]Karim Khordoc, Eduard Cerny:
Modeling Cell Processing Hardware with Action Diagrams. ISCAS 1994: 245-248 - 1993
- [j20]El Mostapha Aboulhamid, Younès Karkouri, Eduard Cerny:
On the generation of test patterns for multiple faults. J. Electron. Test. 4(3): 237-253 (1993) - [c14]Karim Khordoc, Mario Dufresne, Eduard Cerny, P. A. Babkine, Allan Silburt:
Integrating Behavior and Timing in Executable Specifications. CHDL 1993: 399-416 - [c13]Michel Langevin, Eduard Cerny:
A Recursive Technique for Computing Lower-Bound Performance of Schedules. ICCD 1993: 16-20 - 1992
- [j19]Mohamed Meknassi, El Mostapha Aboulhamid, Eduard Cerny:
Algorithm for the graph-partitioning problem using a problem transformation method. Comput. Aided Des. 24(7): 397-398 (1992) - [j18]Eduard Cerny, John P. Hayes, Nicholas C. Rumin:
Accuracy of magnitude-class calculations in switch-level modeling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(4): 443-452 (1992) - [c12]Eduard Cerny:
Verification of I/O Trace Set Inclusion for a Class of Non-Deterministic Finite State Machines. ICCD 1992: 526-530 - 1991
- [j17]Jean Paul Caisso, Eduard Cerny, Nicholas C. Rumin:
A recursive technique for computing delays in series-parallel MOS transistor circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(5): 589-595 (1991) - [c11]Michel Langevin, Eduard Cerny:
Comparing Generic State Machines. CAV 1991: 466-476 - [c10]Anas Kabbaj, Eduard Cerny, Michel R. Dagenais, François Bouthillier:
Design by similarity using transaction modeling and statistical techniques. EURO-DAC 1991: 464-468 - [c9]Karim Khordoc, Mario Dufresne, Eduard Cerny:
A Stimulus/Response System Based on Hierarchical Timing Diagrams. ICCAD 1991: 358-361 - [c8]Eduard Cerny:
A Compositional Transformation for Formal Verification. ICCD 1991: 240-244 - 1990
- [j16]Jianli Sun, Jan Gecsei, Eduard Cerny:
Fault-tolerance in balanced sorting networks. J. Electron. Test. 1(1): 31-41 (1990) - [c7]Eduard Cerny, C. Mauras:
Tautology Checking Using Cross-Controllability and Cross-Observability Relations. ICCAD 1990: 34-37
1980 – 1989
- 1989
- [c6]Eduard Cerny, John P. Hayes, Nicholas C. Rumin:
Magnitude classes in switch-level modeling. ICCD 1989: 284-288 - 1988
- [j15]Eduard Cerny, El Mostapha Aboulhamid, Guy Bois, Jocelyn Cloutier:
Built-in self-test of a CMOS ALU. IEEE Des. Test 5(4): 38-48 (1988) - [j14]Eduard Cerny, Jan Gecsei:
Functional Description of Connector-Switch-Attenuator Networks. IEEE Trans. Computers 37(1): 111-114 (1988) - [j13]Christian Berthet, Eduard Cerny:
An Algebraic Model for Asynchronous Circuits Verification. IEEE Trans. Computers 37(7): 835-847 (1988) - [c5]Mohsine Eleuldj, El Mostapha Aboulhamid, Eduard Cerny:
A class of fault-tolerant cellular permutation networks. ICCD 1988: 136-139 - 1987
- [j12]Jan Gecsei, Eduard Cerny:
Self-Adjusting Networks for VLSI Simulation. IEEE Trans. Computers 36(9): 1114-1120 (1987) - [j11]Behçet Sarikaya, Gregor von Bochmann, Eduard Cerny:
A Test Design Methodology for Protocol Testing. IEEE Trans. Software Eng. 13(5): 518-531 (1987) - [c4]Louis-Philippe Demers
, P. Jacques, S. Fauvel, Eduard Cerny:
CHESHIRE: An Object-Oriented Integration of VLSI CAD Tools. DAC 1987: 750-756 - 1985
- [j10]Eduard Cerny, Jan Gecsei:
Simulation of MOS Circuits by Decision Diagrams. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 4(4): 685-693 (1985) - [c3]C. Roy, Louis-Philippe Demers, Eduard Cerny, Jan Gecsei:
An object-oriented swicth-level simulator. DAC 1985: 623-629 - 1984
- [j9]Eduard Cerny:
Some issues in protocol implementation testing. Comput. Commun. Rev. 14(2): 259-260 (1984) - [j8]El Mostapha Aboulhamid, Eduard Cerny:
Built-In Testing of One-Dimensional Unilateral Iterative Arrays. IEEE Trans. Computers 33(6): 560-564 (1984) - [c2]Gregor von Bochmann, Eduard Cerny, George Walter Gerber, Rachida Dssouli, Michel Maksud, B. H. Phan, Behçet Sarikaya, Jean-Marc Serre:
Use of Formal Specifications for Protocol Design, Implementation and Testing. PSTV 1984: 137-144 - 1983
- [j7]El Mostapha Aboulhamid, Eduard Cerny:
A Class of Test Generators for Built-In Testing. IEEE Trans. Computers 32(10): 957-959 (1983) - 1982
- [j6]Gregor von Bochmann, Eduard Cerny, Michel Gagné, Claude Jard, Alain Léveillé, Clement Lacaille, Michel Maksud, K. S. Raghunathan, Behçet Sarikaya:
Experience with Formal Specifications Using an Extended State Transition Model. IEEE Trans. Commun. 30(12): 2506-2513 (1982) - [c1]Gregor von Bochmann, Eduard Cerny, Michel Gagné, Claude Jard, Alain Léveillé, Clement Lacaille, Michel Maksud, K. S. Raghunathan, Behçet Sarikaya:
Some Experience with the Use of Formal Specifications. PSTV 1982: 171-185
1970 – 1979
- 1979
- [j5]Eduard Cerny, Daniel Mange, Eduardo Sanchez:
Synthesis of Minimal Binary Decision Trees. IEEE Trans. Computers 28(7): 472-482 (1979) - 1978
- [j4]Eduard Cerny:
Controllability and Fault Observability in Modular Combinational Circuits. IEEE Trans. Computers 27(10): 896-903 (1978) - 1977
- [j3]Eduard Cerny, Miguel A. Marin:
An Approach to Unified Methodology of Combinational Switching Circuits. IEEE Trans. Computers 26(8): 745-756 (1977) - 1976
- [j2]Eduard Cerny:
Comments on "Equational Logic". IEEE Trans. Computers 25(1): 102-103 (1976) - 1974
- [j1]Eduard Cerny, Miguel A. Marin:
A Computer Algorithm for the Synthesis of Memoryless Logic Circuits. IEEE Trans. Computers 23(5): 455-465 (1974)
Coauthor Index
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