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ORCIDJournal of Electronic Testing, Volume 1
Volume 1, Number 1, February 1990
- Wu-Tung Cheng, Meng-Lin Yu:
Differential fault simulation for sequential circuits. 7-13 - Srinivas Devadas, Hi-Keung Tony Ma, A. Richard Newton:
Redundancies and don't cares in sequential logic synthesis. 15-30 - Jianli Sun, Jan Gecsei, Eduard Cerny:
Fault-tolerance in balanced sorting networks. 31-41 - Yinan N. Shen, Fabrizio Lombardi:
Yield enhancement and manufacturing throughput of redundant memories by repairability/unrepairability detection. 43-57 - Yervant Zorian, Vinod K. Agarwal:
Optimizing error masking in BIST by output data modification. 59-71 - Paul H. Bardell:
Design considerations for Parallel pseudoRandom Pattern Generators. 73-87
Volume 1, Number 2, May 1990
- Vishwani D. Agrawal:
Editorial. 101 - Debashis Bhattacharya, John P. Hayes:
A hierarchical test generation methodology for digital circuits. 103-123 - Hyoung B. Min, William A. Rogers:
Search strategy switching: A cost model and an analysis of backtracking. 125-137 - Daniel G. Saab, Robert B. Mueller-Thuns, David T. Blaauw, Joseph T. Rahmeh, Jacob A. Abraham:
Hierarchical multi-level fault simulation of large systems. 139-149 - Janusz A. Brzozowski, Bruce F. Cockburn:
Detection of coupling faults in RAMs. 151-162 - Arno Kunzmann, Hans-Joachim Wunderlich:
An analytical approach to the partial scan problem. 163-174 - Wen-Ben Jone, Sunil R. Das:
Multiple-output parity bit signature for exhaustive testing. 175-178
Volume 1, Number 3, October 1990
- Yuzo Takamatsu, Kozo Kinoshita:
Extended selection of switching target faults in CONT algorithm for test generation. 183-189 - Sandip Kundu, Sudhakar M. Reddy:
Robust tests for parity trees. 191-200 - Yoon-Hwa Choi:
Distributed diagnosis for homogeneous systems. 201-211 - Martin Rudolph:
Feedback-testing by using multiple input signature registers. 213-219 - Vishwani D. Agrawal, Kwang-Ting Cheng:
Finite state machine synthesis with embedded test function. 221-228 - Paolo Camurati, Paolo Prinetto, Matteo Sonza Reorda
:
Exact probabilistic testability measures for multi-output circuits. 229-234 - Masahisa Nakazawa, Susumu Nitta, Kanji Hirabayashi:
Probabilistic fault grading based on activation checking and observability analysis. 235-238
Volume 1, Number 4, January 1991
- Asad A. Ismaeel, Melvin A. Breuer:
The probability of error detection in sequential circuits using random test vectors. 245-256 - Michael Nicolaidis:
Shorts in self-checking circuits. 257-273 - Sreejit Chakravarty:
A characterization of robust test-pairs for stuck-open faults. 275-286 - João Paulo Teixeira, Isabel C. Teixeira, Carlos F. Beltrán Almeida, Fernando M. Gonçalves, Júlio Gonçalves:
A methodology for testability enhancement at layout level. 287-299 - I. P. Litikov:
Ring-like testing of digital circuits. 301-304
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