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ORCIDKanji Hirabayashi
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2000 – 2009
- 2001
[j8]Kanji Hirabayashi:
An Algebraic Approach to Formal Verification of Microprocessors. J. Electron. Test. 17(6): 543-544 (2001)
1990 – 1999
- 1998
- [j7]Kanji Hirabayashi:
A Method of Formal Verification of Cryptographic Circuits. J. Electron. Test. 13(3): 321-322 (1998) - 1996
- [j6]Kanji Hirabayashi:
Hazard simulation of sequential circuits. J. Electron. Test. 8(2): 215-217 (1996) - 1995
- [j5]Kanji Hirabayashi:
A parametric yield model. J. Electron. Test. 6(3): 331-332 (1995) - 1993
- [j4]Kanji Hirabayashi:
Delay fault simulation of sequential circuits. J. Electron. Test. 4(2): 131-135 (1993) - 1991
- [j3]Kanji Hirabayashi:
Self-checking CMOS circuits using pass-transistor logic. J. Electron. Test. 2(2): 205-208 (1991) - 1990
- [j2]Masahisa Nakazawa, Susumu Nitta, Kanji Hirabayashi:
Probabilistic fault grading based on activation checking and observability analysis. J. Electron. Test. 1(3): 235-238 (1990)
1980 – 1989
- 1985
- [j1]Susumu Nitta, Masahiko Kawamura, Kanji Hirabayashi:
Test generation by activation and defect-drive (TEGAD). Integr. 3(1): 3-12 (1985) - [c2]Masahiko Kawamura, Kanji Hirabayashi:
AFS : An Approximate Fault Simulator. ITC 1985: 717-721 - 1984
- [c1]Masahiko Kawamura, Haruo Takagi, Kanji Hirabayashi:
Functional verification of memory circuits from mask artwork data. DAC 1984: 228-234
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