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ORCIDMelvin A. Breuer
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- affiliation: University of Southern California, Los Angeles, USA
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2010 – 2019
- 2016
[j72]Yang Zhang
, Leandro S. Heck, Matheus T. Moreira, David Zar, Melvin A. Breuer, Ney Laert Vilar Calazans, Peter A. Beerel:
Testable MUTEX Design. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(8): 1188-1199 (2016)- 2015
- [c117]Dylan Hand, Matheus Trevisan Moreira, Hsin-Ho Huang, Danlei Chen, Frederico Butzke, Zhichao Li, Matheus Gibiluka, Melvin A. Breuer, Ney Laert Vilar Calazans, Peter A. Beerel:
Blade - A Timing Violation Resilient Asynchronous Template. ASYNC 2015: 21-28 - [c116]Dylan Hand, Hsin-Ho Huang, Benmao Cheng, Yang Zhang, Matheus Trevisan Moreira, Melvin A. Breuer, Ney Laert Vilar Calazans, Peter A. Beerel:
Performance Optimization and Analysis of Blade Designs under Delay Variability. ASYNC 2015: 61-68 - [c115]Yang Zhang, Leandro S. Heck, Matheus T. Moreira, David Zar, Melvin A. Breuer, Ney Laert Vilar Calazans, Peter A. Beerel:
Design and Analysis of Testable Mutual Exclusion Elements. ASYNC 2015: 124-131 - [c114]Shuo Wang, Yue Gao, Melvin A. Breuer:
GlYFF: A framework for global yield and floorplan aware design optimization. ISQED 2015: 70-76 - 2013
- [c113]Yue Gao, Sandeep K. Gupta, Melvin A. Breuer:
Using explicit output comparisons for fault tolerant scheduling (FTS) on modern high-performance processors. DATE 2013: 927-932 - [c112]Yue Gao, Melvin A. Breuer, Yanzhi Wang:
A new paradigm for trading off yield, area and performance to enhance performance per wafer. DATE 2013: 1753-1758 - [c111]Yue Gao, Yang Zhang, Da Cheng, Melvin A. Breuer:
Trading off area, yield and performance via hybrid redundancy in multi-core architectures. VTS 2013: 1-6 - 2012
- [j71]Kuen-Jong Lee, Tong-Yu Hsieh, Melvin A. Breuer:
Efficient Overdetection Elimination of Acceptable Faults for Yield Improvement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(5): 754-764 (2012) - [j70]Zhaoliang Pan, Melvin A. Breuer:
Error Rate Estimation for Defective Circuits via Ones Counting. ACM Trans. Design Autom. Electr. Syst. 17(1): 8:1-8:14 (2012) - [c110]Mohammad Mirza-Aghatabar, Melvin A. Breuer, Sandeep K. Gupta, Shahin Nazarian:
Theory of redundancy for logic circuits to maximize yield/area. ISQED 2012: 663-671 - [c109]Mohammad Mirza-Aghatabar, Melvin A. Breuer, Sandeep K. Gupta:
A design flow to maximize yield/area of physical devices via redundancy. ITC 2012: 1-10 - 2011
- [j69]Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer:
An Error-Tolerance-Based Test Methodology to Support Product Grading for Yield Enhancement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(6): 930-934 (2011) - 2010
- [c108]Mohammad Mirza-Aghatabar, Melvin A. Breuer, Sandeep K. Gupta:
HYPER: A Heuristic for Yield/Area imProvEment Using Redundancy in SoC. Asian Test Symposium 2010: 249-254 - [c107]Melvin A. Breuer:
Hardware that produces bounded rather than exact results. DAC 2010: 871-876 - [c106]Mohammad Mirza-Aghatabar, Melvin A. Breuer, Sandeep K. Gupta:
Algorithms to maximize yield and enhance yield/area of pipeline circuitry by insertion of switches and redundant modules. DATE 2010: 1249-1254
2000 – 2009
- 2009
- [c105]Mohammad Mirza-Aghatabar, Melvin A. Breuer, Sandeep K. Gupta:
SIRUP: Switch Insertion in RedUndant Pipeline Structures for Yield and Yield/Area Improvement. Asian Test Symposium 2009: 193-199 - [c104]Tong-Yu Hsieh, Melvin A. Breuer, Murali Annavaram, Sandeep K. Gupta, Kuen-Jong Lee:
Tolerance of performance degrading faults for effective yield improvement. ITC 2009: 1-10 - 2008
- [j68]Melvin A. Breuer, Haiyang (Henry) Zhu:
An Illustrated Methodology for Analysis of Error Tolerance. IEEE Des. Test Comput. 25(2): 168-177 (2008) - [j67]Melvin A. Breuer:
Clarifying the record on testability cost functions. IEEE Des. Test Comput. 25(6): 608-609 (2008) - [j66]Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer:
An Error Rate Based Test Methodology to Support Error-Tolerance. IEEE Trans. Reliab. 57(1): 204-214 (2008) - [c103]Arani Sinha, Sandeep K. Gupta, Melvin A. Breuer:
A Multi-valued Algebra for Capacitance Induced Crosstalk Delay Faults. ATS 2008: 89-96 - [c102]Zhaoliang Pan, Melvin A. Breuer:
Basing Acceptable Error-Tolerant Performance on Significance-Based Error-rate (SBER). VTS 2008: 59-66 - 2007
- [j65]Zhaoliang Pan, Melvin A. Breuer:
Estimating Error Rate in Defective Logic Using Signature Analysis. IEEE Trans. Computers 56(5): 650-661 (2007) - [c101]Shahdad Irajpour, Sandeep K. Gupta, Melvin A. Breuer:
Improving Timing-Independent Testing of Crosstalk Using Realistic Assumptions on Delay Faults. ATS 2007: 57-64 - [c100]Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer:
Reduction of detected acceptable faults for yield improvement via error-tolerance. DATE 2007: 1599-1604 - 2006
- [c99]Lei Wang, Sandeep K. Gupta, Melvin A. Breuer:
Diagnosis of delay faults due to resistive bridges, delay variations and defects. ATS 2006: 215-224 - [c98]Shahdad Irajpour, Sandeep K. Gupta, Melvin A. Breuer:
Test Generation for Weak Resistive Bridges. ATS 2006: 265-272 - [c97]Shahin Nazarian, Massoud Pedram, Sandeep K. Gupta, Melvin A. Breuer:
STAX: statistical crosstalk target set compaction. DATE Designers' Forum 2006: 172-177 - [c96]Melvin A. Breuer, Haiyang (Henry) Zhu:
Error-Tolerance and Multi-Media. IIH-MSP 2006: 521-524 - [c95]Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer:
An Error-Oriented Test Methodology to Improve Yield with Error-Tolerance. VTS 2006: 130-135 - 2005
- [c94]Melvin A. Breuer:
Multi-media Applications and Imprecise Computation. DSD 2005: 2-7 - [c93]Melvin A. Breuer:
Let's Think Analog. ISVLSI 2005: 2-5 - [c92]Shahdad Irajpour, Sandeep K. Gupta, Melvin A. Breuer:
Multiple tests for each gate delay fault: higher coverage and lower test application cost. ITC 2005: 9 - [c91]Kuen-Jong Lee, Tong-Yu Hsieh, Melvin A. Breuer:
A novel test methodology based on error-rate to support error-tolerance. ITC 2005: 9 - 2004
- [j64]Melvin A. Breuer, Sandeep K. Gupta, T. M. Mak:
Defect and Error Tolerance in the Presence of Massive Numbers of Defects. IEEE Des. Test Comput. 21(3): 216-227 (2004) - [c90]Melvin A. Breuer, Sandeep K. Gupta, Shahin Nazarian:
Efficient Identification of Crosstalk Induced Slowdown Targets. Asian Test Symposium 2004: 124-131 - [c89]Melvin A. Breuer:
Intelligible Test Techniques to Support Error-Tolerance. Asian Test Symposium 2004: 386-393 - [c88]Lei Wang, Sandeep K. Gupta, Melvin A. Breuer:
Modeling and Simulation for Crosstalk Aggravated by Weak-Bridge Defects between On-Chip Interconnects. Asian Test Symposium 2004: 440-447 - [c87]Melvin A. Breuer:
Determining error rate in error tolerant VLSI chips. DELTA 2004: 321-326 - [c86]Shahdad Irajpour, Sandeep K. Gupta, Melvin A. Breuer:
Timing-Independent Testing of Crosstalk in the Presence of Delay Producing Defects Using Surrogate Fault Models. ITC 2004: 1024-1033 - 2003
- [c85]Arani Sinha, Sandeep K. Gupta, Melvin A. Breuer:
An Enhanced Test Generator for Capacitance Induced Crosstalk Delay Faults. Asian Test Symposium 2003: 174-177 - [c84]Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer:
Test Generation for Maximizing Ground Bounce Considering Circuit Delay. VTS 2003: 151-157 - [c83]Shahdad Irajpour, Shahin Nazarian, Lei Wang, Sandeep K. Gupta, Melvin A. Breuer:
Analyzing Crosstalk in the Presence of Weak Bridge Defects. VTS 2003: 385-392 - 2002
- [j63]Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer:
Test Generation for Crosstalk-Induced Faults: Framework and Computational Results. J. Electron. Test. 18(1): 17-28 (2002) - [j62]Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer:
TA-PSV - Timing Analysis for Partially Specified Vectors. J. Electron. Test. 18(1): 73-88 (2002) - [j61]Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer:
Analytical models for crosstalk excitation and propagation in VLSI circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(10): 1117-1131 (2002) - [c82]I-De Huang, Sandeep K. Gupta, Melvin A. Breuer:
Accurate and Efficient Static Timing Analysis with Crosstalk. ICCD 2002: 265-272 - [c81]Shahin Nazarian, Hang Huang, Suriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer:
XIDEN: Crosstalk Target Identification Framework. ITC 2002: 365-374 - 2001
- [j60]Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer:
Introducing redundant computations in RTL data paths for reducing BIST resources. ACM Trans. Design Autom. Electr. Syst. 6(3): 423-445 (2001) - [c80]Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer:
A New Gate Delay Model for Simultaneous Switching and Its Applications. DAC 2001: 289-294 - [c79]Suriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer:
Switch-level delay test of domino logic circuits. ITC 2001: 367-376 - [c78]Liang-Chi Chen, T. M. Mak, Sandeep K. Gupta, Melvin A. Breuer:
Crosstalk test generation on pseudo industrial circuits: a case study. ITC 2001: 548-557 - [c77]Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer:
Test Generation for Maximizing Ground Bounce for Internal Circuitry with Reconvergent Fan-out. VTS 2001: 358-367 - 2000
- [j59]Rajagopalan Srinivasan, Sandeep K. Gupta, Melvin A. Breuer:
Novel Test Pattern Generators for Pseudoexhaustive Testing. IEEE Trans. Computers 49(11): 1228-1240 (2000) - [j58]Melvin A. Breuer, Majid Sarrafzadeh, Fabio Somenzi:
Fundamental CAD algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(12): 1449-1475 (2000) - [c76]Melvin A. Breuer, Kwang-Ting Cheng:
Challenges for the Academic Test Community. Asian Test Symposium 2000: 4 - [c75]Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer:
A new framework for static timing analysis, incremental timing refinement, and timing simulation. Asian Test Symposium 2000: 102-107 - [c74]Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer:
Test generation for crosstalk-induced faults: framework and computational result. Asian Test Symposium 2000: 305-310 - [c73]Melvin A. Breuer, Sandeep K. Gupta:
New Validation and Test Problems for High Performance Deep Submicron VLSI Circuits. VLSI Design 2000: 8 - [c72]Melvin A. Breuer:
High End and Low End Applications for Defective Chips: Enhanced Availability and Acceptability. VTS 2000: 473-474
1990 – 1999
- 1999
- [c71]Arani Sinha, Sandeep K. Gupta, Melvin A. Breuer:
Validation and test generation for oscillatory noise in VLSI interconnects. ICCAD 1999: 289-296 - [c70]Suriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer:
Switch-level delay test. ITC 1999: 171-180 - [c69]Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer:
Test generation for crosstalk-induced delay in integrated circuits. ITC 1999: 191-200 - [c68]Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer:
Test Generation for Ground Bounce in Internal Logic Circuitry. VTS 1999: 95-105 - 1998
- [j57]Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer:
Allocation Techniques for Reducing BIST Area Overhead of Data Paths. J. Electron. Test. 13(2): 149-166 (1998) - [j56]Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer:
Estimation of BIST Resources During High-Level Synthesis. J. Electron. Test. 13(3): 221-237 (1998) - [j55]Debaditya Mukherjee, Melvin A. Breuer:
An IEEE 1149.1 Compliant Test Control Architecture. J. Electron. Test. 13(3): 273-297 (1998) - [j54]Rajagopalan Srinivasan, Sandeep K. Gupta, Melvin A. Breuer:
Bounds on pseudoexhaustive test lengths. IEEE Trans. Very Large Scale Integr. Syst. 6(3): 420-431 (1998) - [c67]Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer:
Introducing Redundant Computations in a Behavior for Reducing BIST Resources. DAC 1998: 548-553 - [c66]Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer:
Scheduling and Module Assignment for Reducing Bist Resources. DATE 1998: 66-73 - [c65]Suriyaprakash Natarajan, Melvin A. Breuer, Sandeep K. Gupta:
Process Variations and their Impact on Circuit Operation. DFT 1998: 73- - [c64]Weiyu Chen, Sandeep K. Gupta, Melvin A. Breuer:
Test generation in VLSI circuits for crosstalk noise. ITC 1998: 641-650 - 1997
- [c63]Weiyu Chen, Melvin A. Breuer, Sandeep K. Gupta:
Analytic Models for Crosstalk Delay and Pulse Analysis Under Non-Ideal Inputs. ITC 1997: 809-818 - [c62]Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer:
High Quality Robust Tests for Path Delay Faults. VTS 1997: 88-93 - [c61]Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer:
Analysis of Ground Bounce in Deep Sub-Micron Circuits. VTS 1997: 110-116 - [c60]Melvin A. Breuer, Bozena Kaminska, John E. McDermid, V. Rayapathi, Donald L. Wheater:
Will 0.1um Digital Circuits Require Mixed-Signal Testing. VTS 1997: 186-187 - 1996
- [c59]Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer:
Lower Bounds on Test Resources for Scheduled Data Flow Graphs. DAC 1996: 143-148 - [c58]Melvin A. Breuer, Sandeep K. Gupta:
Process-Aggravated Noise (PAN): New Validation and Test Problems. ITC 1996: 914-923 - 1995
- [j53]Rajesh Gupta, Melvin A. Breuer:
Partial scan design of register-transfer level circuits. J. Electron. Test. 7(1-2): 25-46 (1995) - [j52]Mody Lempel, Sandeep K. Gupta, Melvin A. Breuer:
Test embedding with discrete logarithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(5): 554-566 (1995) - [j51]Sridhar Narayanan, Melvin A. Breuer:
Reconfiguration techniques for a single scan chain. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(6): 750-765 (1995) - [j50]Kuen-Jong Lee, Chih-Nan Wang, Rajiv Gupta, Melvin A. Breuer:
An integrated system for assigning signal flow directions to CMOS transistors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(12): 1445-1458 (1995) - [c57]Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer:
Data Path Allocation for Synthesizing RTL Designs with Low BIST Area Overhead. DAC 1995: 395-401 - [c56]Sridhar Narayanan, Melvin A. Breuer:
Asynchronous multiple scan chain. VTS 1995: 270-276 - 1994
- [j49]Kuen-Jong Lee, Charles Njinda, Melvin A. Breuer:
SWiTEST: a switch level test generation system for CMOS combinational circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(5): 625-637 (1994) - [c55]Ishwar Parulkar, Melvin A. Breuer, Charles Njinda:
Extraction of a High-level structural Representation from Circuit Descriptions with Applications to DFT/BIST. DAC 1994: 345-356 - [c54]Sen-Pin Lin, Sandeep K. Gupta, Melvin A. Breuer:
A Low Cost BIST Methodology and Associated Novel Test Pattern Generator. EDAC-ETC-EUROASIC 1994: 106-112 - [c53]Debaditya Mukherjee, Massoud Pedram, Melvin A. Breuer:
Control Strategies for Chip-Based DFT/BIST Hardware. ITC 1994: 893-902 - [c52]Mody Lempel, Sandeep K. Gupta, Melvin A. Breuer:
Test embedding with discrete logarithms. VTS 1994: 74-80 - 1993
- [j48]Sen-Pin Lin, Charles Njinda, Melvin A. Breuer:
Generating a family of testable designs using the BILBO methodology. J. Electron. Test. 4(1): 71-89 (1993) - [j47]Jung-Cheun Lien, Melvin A. Breuer:
Test program synthesis for modules and chips having boundary scan. J. Electron. Test. 4(2): 159-180 (1993) - [j46]Sridhar Narayanan, Rajesh Gupta, Melvin A. Breuer:
Optimal Configuring of Multiple Scan Chains. IEEE Trans. Computers 42(9): 1121-1131 (1993) - [c51]Rajagopalan Srinivasan, Sandeep K. Gupta, Melvin A. Breuer:
An Efficient Partitioning Strategy for Pseudo-Exhaustive Testing. DAC 1993: 242-248 - [c50]Sridhar Narayanan, Melvin A. Breuer:
Reconfigurable scan chains: a novel approach to reduce test application time. ICCAD 1993: 710-715 - [c49]Debaditya Mukherjee, Massoud Pedram, Melvin A. Breuer:
Merging multiple FSM controllers for DFT/BIST hardware. ICCAD 1993: 720-725 - [c48]Rajagopalan Srinivasan, Sandeep K. Gupta, Melvin A. Breuer:
Novel Test Pattern Generators for Pseudo-Exhaustive Testing. ITC 1993: 1041-1050 - 1992
- [j45]Kuen-Jong Lee, Melvin A. Breuer:
Design and test rules for CMOS circuits to facilitate IDDQ testing of bridging faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(5): 659-670 (1992) - [c47]Kuen-Jong Lee, Charles Njinda, Melvin A. Breuer:
SWiTEST: A Switch Level Test Generation System for CMOS Combinational Circuits. DAC 1992: 26-29 - [c46]Sridhar Narayanan, Charles Njinda, Rajesh Gupta, Melvin A. Breuer:
SIESTA: a multi-facet scan design system. EURO-DAC 1992: 246-251 - [c45]Debaditya Mukherjee, Massoud Pedram, Melvin A. Breuer:
Minimal area merger of finite state machine controllers. EURO-DAC 1992: 278-283 - [c44]Sridhar Narayanan, Rajesh Gupta, Melvin A. Breuer:
Configuring multiple scan chains for minimum test time. ICCAD 1992: 4-8 - [c43]Sridhar Narayanan, Charles Njinda, Melvin A. Breuer:
Optimal Sequencing of Scan Registers. ITC 1992: 293-302 - [c42]Rajesh Gupta, Melvin A. Breuer:
Testability properties of acyclic structures and applications to partial scan design. VTS 1992: 49-54 - 1991
- [j44]Rajiv Gupta, Rajagopalan Srinivasan, Melvin A. Breuer:
Reorganizing Circuits to Aid Testability. IEEE Des. Test Comput. 8(3): 49-57 (1991) - [j43]Asad A. Ismaeel, Melvin A. Breuer:
The probability of error detection in sequential circuits using random test vectors. J. Electron. Test. 1(4): 245-256 (1991) - [j42]Jung-Cheun Lien, Melvin A. Breuer:
An optimal scheduling algorithm for testing interconnect using boundary scan. J. Electron. Test. 2(1): 117-130 (1991) - [c41]Debaditya Mukherjee, Charles Njinda, Melvin A. Breuer:
Synthesis of Optimal 1-Hot Coded On-Chip Controllers for BIST Hardware. ICCAD 1991: 236-239 - [c40]Rajesh Gupta, Melvin A. Breuer:
Ordering Storage Elements in a Single Scan Chain. ICCAD 1991: 408-411 - [c39]Sen-Pin Lin, Charles Njinda, Melvin A. Breuer:
A Systematic Approach for Designing Testable VLSI Circuits. ICCAD 1991: 496-499 - [c38]Jung-Cheun Lien, Melvin A. Breuer:
Maximal Diagnosis for Wiring Networks. ITC 1991: 96-105 - [c37]Rajagopalan Srinivasan, Charles Njinda, Melvin A. Breuer:
A partitioning method for achieving maximal test concurrency in pseudo-exhaustive testing. VTS 1991: 34-39 - [c36]Kuen-Jong Lee, Melvin A. Breuer:
Constraints for using IDDQ testing to detect CMOS bridging faults. VTS 1991: 303-308 - 1990
- [b1]Miron Abramovici, Melvin A. Breuer, Arthur D. Friedman:
Digital systems testing and testable design. Computer Science Press 1990, ISBN 978-0-7167-8179-0, pp. I-XXI, 1-653 - [j41]Amitava Majumdar, Cauligi S. Raghavendra, Melvin A. Breuer:
Fault Tolerance in Linear Systolic Arrays Using Time Redundancy. IEEE Trans. Computers 39(2): 269-276 (1990) - [j40]Rajesh Gupta, Rajiv Gupta, Melvin A. Breuer:
The BALLAST Methodology for Structured Partial Scan Design. IEEE Trans. Computers 39(4): 538-544 (1990) - [c35]Kuen-Jong Lee, Rajiv Gupta, Melvin A. Breuer:
A New Method for Assigning Signal Flow Directions to MOS Transistors. ICCAD 1990: 492-495 - [c34]Rajiv Gupta, Melvin A. Breuer:
An Extensible User Interface for an Object-Oriented VLSI CAD Framework. ICSI 1990: 559-568 - [c33]Melvin A. Breuer:
Obstacles and an approach towards concurrent engineering. ITC 1990: 260-261 - [c32]Kuen-Jong Lee, Melvin A. Breuer:
On the charge sharing problem in CMOS stuck-open fault testing. ITC 1990: 417-426
1980 – 1989
- 1989
- [j39]Rajiv Gupta, Wesley H. Cheng, Rajesh Gupta, Ido Hardonag, Melvin A. Breuer:
An Object-Oriented VLSI CAD Framework: A Case Study in Rapid Prototyping. Computer 22(5): 28-37 (1989) - [j38]Mandalagiri S. Chandrasekhar, Melvin A. Breuer:
Optimal routing of two rectangular blocks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(4): 413-430 (1989) - [c31]Rajesh Gupta, Rajiv Gupta, Melvin A. Breuer:
BALLAST: a methodology for partial scan design. FTCS 1989: 118-125 - 1988
- [j37]Xi-an Zhu, Melvin A. Breuer:
Analysis of testable PLA designs. IEEE Des. Test 5(4): 14-28 (1988) - [j36]Xi-an Zhu, Melvin A. Breuer:
A knowledge-based system for selecting test methodologies. IEEE Des. Test 5(5): 41-59 (1988) - [j35]Salim U. Chowdhury, Melvin A. Breuer:
Optimum design of IC power/ground nets subject to reliability constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(7): 787-796 (1988) - [j34]Sarma Sastry, Melvin A. Breuer:
Detectability of CMOS stuck-open faults using random and pseudorandom test sequences. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(9): 933-946 (1988) - [c30]Melvin A. Breuer, Wesley H. Cheng, Rajiv Gupta, Ido Hardonag, Ellis Horowitz, S. Y. Lin:
Cbase 1.0: a CAD database for VLSI circuits using object oriented technology. ICCAD 1988: 392-395 - [c29]B. Sharma, Rajiv Jain, Melvin A. Breuer, Alice C. Parker, Cauligi S. Raghavendra, C. Y. Tseng:
The POTATO chip architecture: a study in tradeoffs for signal processing chip design. ICCD 1988: 508-513 - [c28]Melvin A. Breuer, Amitava Majumdar, Cauligi S. Raghavendra:
Fault tolerance and testing aspects of an architecture for a generalized sidelobe cancellor. ICCD 1988: 514-519 - [c27]Sandeep K. Gupta, Melvin A. Breuer, Jung-Cheun Lien:
Concurrent Control of Multiple BIT Structures. ITC 1988: 431-442 - [c26]Melvin A. Breuer, Jung-Cheun Lien:
A Test and Maintenance Controller for a Module Containing Testable Chips. ITC 1988: 502-513 - 1987
- [j33]Melvin A. Breuer, F. Saheban:
Built-in test for folded programmable logic arrays. Microprocess. Microsystems 11(6): 319-329 (1987) - 1986
- [j32]Salim U. Chowdhury, Melvin A. Breuer:
An O(n) algorithm for width determination of power/ground routes for VLSI circuits. Integr. 4(4): 345-355 (1986) - [j31]Magdy S. Abadir, Melvin A. Breuer:
Test Schedules for VLSI Circuits Having Built-In Test Hardware. IEEE Trans. Computers 35(4): 361-367 (1986) - [j30]Melvin A. Breuer, Asad A. Ismaeel:
Roving Emulation as a Fault Detection Mechanism. IEEE Trans. Computers 35(11): 933-939 (1986) - [c25]Xi-an Zhu, Melvin A. Breuer:
A Knowledge-Based TDM Selection System. FJCC 1986: 854-863 - [c24]Magdy S. Abadir, Melvin A. Breuer:
Scan Path with Look Ahead Shifting (SPLASH). ITC 1986: 696-704 - 1985
- [j29]Magdy S. Abadir, Melvin A. Breuer:
A Knowledge-Based System for Designing Testable VLSI Chips. IEEE Des. Test 2(4): 56-68 (1985) - [j28]Ting-Hua Chen, Melvin A. Breuer:
Automatic Design for Testability Via Testability Measures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 4(1): 3-11 (1985) - [c23]Melvin A. Breuer, Xi-an Zhu:
A knowledge based system for selecting a test methodology for a PLA. DAC 1985: 259-265 - [c22]Salim U. Chowdhury, Melvin A. Breuer:
The construction of minimal area power and ground nets for VLSI circuits. DAC 1985: 794-797 - 1984
- [j27]Israel Koren, Melvin A. Breuer:
On Area and Yield Considerations for Fault-Tolerant VLSI Processor Arrays. IEEE Trans. Computers 33(1): 21-27 (1984) - 1983
- [j26]Harold W. Carter, Melvin A. Breuer:
Efficient Single-Layer Routing Along a Line of Points. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2(4): 259-266 (1983) - [j25]Melvin A. Breuer, Anshul Kumar:
A methodology for custom VLSI layout. IEEE Trans. Syst. Man Cybern. 13(4): 470-476 (1983) - [c21]Alexander Iosupovicz, Clarence King, Melvin A. Breuer:
A module interchange placement machine. DAC 1983: 171-174 - [c20]Dah-Juh Chyan, Melvin A. Breuer:
A placement algorithm for array processors. DAC 1983: 182-188 - 1982
- [j24]Miron Abramovici, Melvin A. Breuer:
Fault Diagnosis in Synchronous Sequential Circuits Based on an Effect-Cause Analysis. IEEE Trans. Computers 31(12): 1165-1172 (1982) - [c19]Melvin A. Breuer:
A survey of the state-of-the-art of design automation an invited presentation. DAC 1982: 1 - [c18]Mandalagiri S. Chandrasekhar, Melvin A. Breuer:
Optimum placement of two rectangular blocks. DAC 1982: 879-886 - [c17]Zahir A. Syed, Abbas El Gamal, Melvin A. Breuer:
On routing for custom integrated circuits. DAC 1982: 887-893 - 1981
- [j23]Melvin A. Breuer, Arthur D. Friedman, Alexander Iosupovicz:
A Survey of the State of the Art of Design Automation. Computer 14(10): 58-75 (1981) - [j22]Sarangan Krishna Kumar, Melvin A. Breuer:
Probabilistic Aspects of Boolean Switching Functions via a New Transform. J. ACM 28(3): 502-520 (1981) - [c16]Melvin A. Breuer, Alice C. Parker:
Digital system simulation: Current status and future trends or darwin's theory of simulation. DAC 1981: 269-275 - 1980
- [j21]Prathima Agrawal, Melvin A. Breuer:
A probabilistic model for the analysis of the routing process for circuits. Networks 10(2): 111-127 (1980) - [j20]Melvin A. Breuer, Arthur D. Friedman:
Functional Level Primitives in Test Generation. IEEE Trans. Computers 29(3): 223-235 (1980) - [j19]Miron Abramovici, Melvin A. Breuer:
Multiple Fault Diagnosis in Combinational Circuits Based on an Effect-Cause Analysis. IEEE Trans. Computers 29(6): 451-460 (1980) - [c15]Miron Abramovici, Melvin A. Breuer:
Fault diagnosis based on effect-cause analysis: An introduction. DAC 1980: 69-76
1970 – 1979
- 1979
- [j18]Prathima Agrawal, Melvin A. Breuer:
Experiments with a Density Router for PC Cards. IEEE Trans. Computers 28(3): 262-267 (1979) - [j17]Miron Abramovici, Melvin A. Breuer:
On Redundancy and Fault Detection in Sequential Circuits. IEEE Trans. Computers 28(11): 864-865 (1979) - [c14]Harold W. Carter, Melvin A. Breuer, Zahir A. Syed:
Incremental processing applied to Steinberg's placement procedure. DAC 1979: 26-31 - 1978
- [c13]Ytzhak H. Levendel, Melvin A. Breuer:
Mathematical properties of Boolean transformations. MVL 1978: 163-170 - [c12]Ytzhak H. Levendel, Melvin A. Breuer:
Vector representation of switching and three-valued functions. MVL 1978: 202-207 - 1977
- [c11]Danny C. C. Ko, Melvin A. Breuer:
The design of self-checking multi-output combinational circuits. AFIPS National Computer Conference 1977: 711-721 - [c10]Prathima Agrawal, Melvin A. Breuer:
Some theoretical aspects of algorithmic routing. DAC 1977: 23-31 - [c9]Miron Abramovici, Melvin A. Breuer, K. Kumar:
Concurrent fault simulation and functional level modeling. DAC 1977: 128-137 - [c8]Melvin A. Breuer:
A class of min-cut placement algorithms. DAC 1977: 284-290 - 1976
- [j16]Melvin A. Breuer, Shih-Jeh Chang, Stephen Y. H. Su:
Identification of Multiple Stuck-Type Faults in Combinational Networks. IEEE Trans. Computers 25(1): 44-54 (1976) - 1974
- [j15]Melvin A. Breuer, R. Loyd Harrison:
Procedures for Eliminating Static and Dynamic Hazards in Test Generation. IEEE Trans. Computers 23(10): 1069-1078 (1974) - [j14]Melvin A. Breuer:
The Effects of Races, Delays, and Delay Faults on Test Generation. IEEE Trans. Computers 23(10): 1078-1092 (1974) - [c7]Melvin A. Breuer:
Curriculum on design automation at the University of Southern California. ACM Annual Conference (2) 1974: 422-425 - [c6]Melvin A. Breuer, Arthur D. Friedman:
Initial design concepts for an advanced design automation system. DAC 1974: 366-371 - 1973
- [j13]Melvin A. Breuer:
Testing for Intermittent Faults in Digital Circuits. IEEE Trans. Computers 22(3): 241-246 (1973) - 1972
- [j12]Melvin A. Breuer:
Recent Developments in Design Automation. Computer 5(3): 23-35 (1972) - [j11]Melvin A. Breuer:
Generation of Fault Tests for Linear Logic Networks. IEEE Trans. Computers 21(1): 79-83 (1972) - [j10]Melvin A. Breuer:
A Note on Three-Valued Logic Simulation. IEEE Trans. Computers 21(4): 399-402 (1972) - 1971
- [j9]Melvin A. Breuer:
A Random and an Algorithmic Technique for Fault Detection Test Generation for Sequential Circuits. IEEE Trans. Computers 20(11): 1364-1370 (1971) - 1970
- [j8]Melvin A. Breuer:
Simplification of the Covering Problem with Application to Boolean Expressions. J. ACM 17(1): 166-181 (1970) - [j7]Melvin A. Breuer:
Functional Partitioning and Simulation of Digital Circuits. IEEE Trans. Computers 19(11): 1038-1046 (1970)
1960 – 1969
- 1969
- [j6]Melvin A. Breuer:
Generation of optimal code for expressions via factorization. Commun. ACM 12(6): 333-340 (1969) - [j5]Melvin A. Breuer:
Combinatorial Equivalence of (0, 1) Circulant Matrices. J. Comput. Syst. Sci. 3(1): 8-23 (1969) - 1968
- [c5]Melvin A. Breuer:
Heuristic switching expression simplification. ACM National Conference 1968: 241-250 - [c4]Melvin A. Breuer:
Hardware fault detection. AFIPS Fall Joint Computing Conference (2) 1968: 1502-1503 - [c3]Melvin A. Breuer:
Fault Detection in a Linear Cascade of Identical Machines. SWAT 1968: 235-243 - 1967
- [j4]Melvin A. Breuer:
Adaptive Computers. Inf. Control. 11(4): 402-422 (1967) - 1966
- [j3]Melvin A. Breuer:
Coding the vertexes of a graph. IEEE Trans. Inf. Theory 12(2): 148-153 (1966) - [c2]Melvin A. Breuer:
The application of integer programming in design automation. DAC 1966 - 1965
- [j2]Melvin A. Breuer:
Implementation of Threshold Nets by Integer Linear Programming. IEEE Trans. Electron. Comput. 14(6): 950-952 (1965) - 1964
- [j1]Melvin A. Breuer:
Techniques for the simulation of computer logic. Commun. ACM 7(7): 443-446 (1964) - 1962
- [c1]Melvin A. Breuer:
Computer design: The minimization of Boolean functions containing unequal and nonlinear cost functions. ACM National Conference 1962: 116-117
Coauthor Index
[c113] [c110] [c109] [c108] [c106] [c105] [c104] [c103] [c101] [c99] [c98] [c97] [c92] [j64] [c90] [c88] [c86] [c85] [c84] [c83] [j63] [j62] [j61] [c82] [c81] [j60] [c80] [c79] [c78] [c77] [j59] [c75] [c74] [c73] [c71] [c70] [c69] [c68] [j57] [j56] [j54] [c67] [c66] [c65] [c64] [c63] [c62] [c61] [c59] [c58] [j52] [c57] [c54] [c52] [c51] [c48] [c27]
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