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ORCIDMatheus Gibiluka
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2010 – 2019
- 2016
[c7]Ramy N. Tadros, Weizhe Hua, Matheus Gibiluka, Matheus T. Moreira, Ney Laert Vilar Calazans
, Peter A. Beerel:
Analysis and Design of Delay Lines for Dynamic Voltage Scaling Applications. ASYNC 2016: 11-18- [c6]Felipe Todeschini Bortolon, Sergio Johann Filho, Matheus Gibiluka, Sergio Bampi, Ney Laert Vilar Calazans, Fabiano Passuelo Hessel, Matheus Trevisan Moreira:
Design and analysis of the HF-RISC processor targeting voltage scaling applications. SBCCI 2016: 1-6 - [c5]Matheus Gibiluka, Matheus Trevisan Moreira, Walter Lau Neto, Ney Laert Vilar Calazans:
A standard cell characterization flow for non-standard voltage supplies. SBCCI 2016: 1-6 - 2015
- [c4]Dylan Hand, Matheus Trevisan Moreira, Hsin-Ho Huang, Danlei Chen, Frederico Butzke, Zhichao Li, Matheus Gibiluka, Melvin A. Breuer, Ney Laert Vilar Calazans, Peter A. Beerel:
Blade - A Timing Violation Resilient Asynchronous Template. ASYNC 2015: 21-28 - [c3]Matheus Gibiluka, Matheus Trevisan Moreira, Ney Laert Vilar Calazans:
A Bundled-Data Asynchronous Circuit Synthesis Flow Using a Commercial EDA Framework. DSD 2015: 79-86 - [c2]Matheus Gibiluka, Matheus Trevisan Moreira, Fernando Gehm Moraes, Ney Laert Vilar Calazans:
BAT-Hermes: A transition-signaling bundled-data NoC router. LASCAS 2015: 1-4 - 2013
- [c1]Matheus T. Moreira, Felipe G. Magalhaes, Matheus Gibiluka, Fabiano Hessel, Ney Laert Vilar Calazans:
BaBaNoC: An asynchronous network-on-chip described in Balsa. RSP 2013: 37-43
Coauthor Index
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